Dr. Benton Calhoun
Ben received his B.S. degree in electrical engineering with a concentration in computer science from the University of Virginia, Charlottesville, VA, in 2000. He received the M.S. degree and Ph.D. degree in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA, in 2002 and 2006, respectively. In January 2006, he joined the faculty at the University of Virginia in the Electrical and Computer Engineering Department, where he is now a Professor. His research interests include body sensor node (BSN) design, low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and low energy electronics for medical applications.
Ningxi received his BE in Microelectronics from Sun Yat-Sen University in 2011 and MS in Microelectronics and Solid State Electronics from Fudan University, China in 2014. He joined the RLP-VLSI group in August of 2014 and is working towards a PhD in Electrical Engineering. His research interest is SRAM design.
Shuo received his BE in Integrated Circuit Design and Integrated System from University of Electronic Science and Technology of China in 2013 and MS in Microelectronics and Solid State Electronics from Fudan University in 2016. He joined the RLP-VLSI group in July 2016 and is working towards his PhD in Electrical Engineering. His research interests include high efficiency energy harvester, ultra-low-power sensor interface and self-powered IoT SoC.
Daniel received his BS in Electrical Engineering from the University of Central Florida in 2016. He joined the RLP-VLSI group in August 2016 and is working towards his PhD in Electrical Engineering. His research interests include low power circuit design, circuit and system modeling, and tunneling FETs.
Jacob received his BS in Electrical Engineering from the University of Virginia in 2015. He started working with the RLP-VLSI group as an undergraduate for his senior design thesis in 2014 and officially joined the group in May 2015. He is currently working towards his MS in Electrical Engineering.
Henry received his BS in Electrical Engineering from the University of Virginia in the Fall of 2016. He joined the RLP-VLSI group after finishing his undergraduate degree. Henry is currently working towards his PhD in Electrical Engineering.
Rishika received her BE in Electronics and Instrumentation from Medicaps Institute of Technology in 2014, and MS in Electrical Engineering from University of Texas at Dallas in 2016. She continued to work as an RFIC Product Engineer for Qualcomm, San Diego before joining the RLP-VLSI group as a PhD student in June 2017.
Sumanth received his Bachelors degree in Electrical and Electronics from SV University and Masters in VLSI Design from VIT University, India in 2012 and 2015 respectively. He worked as Back-end Design-Automation Engineer in Microchip Technology, India for two years before joining the RLP-VLSI group in July 2017. Sumanth is currently working towards his PhD in Electrical Engineering.
Anjana received his BS degree and MS degree in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST), South Korea, in 2015 and 2017, respectively. He briefly worked as a researcher at KAIST before joining RLP-VLSI group as a PhD candidate in August 2017. His research interests include ultra-low power and ultra-wide band RFIC design.
Peng received her BE in Instrumentation and Optoelectronic Engineering from Beihang University in June 2017. She joined the RLP-VLSI group in August 2017. Peng is currently working towards her PhD in Electrical Engineering.
Shourya received his B.Tech degree in Electronics and Communication Engineering from GGSIP University, New Delhi in June 2017. He joined the RLP-VLSI group in July 2018. Shourya is currently working towards his PhD in Electrical Engineering.
Sudipta received his B.Sc. in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology (BUET) in 2014, and MS in Electrical Engineering from Duke University in 2018. He was an intern in TSMC, San Jose, California. He joined RLP-VLSI Lab as a PhD candidate from July, 2018.
|Dilip Vasudevan||Research Scientist, 2015-2016||Berkeley Labs|
|Kevin Leach||Research Scientist, 01/2017-08/2017||Senior Research Fellow, UMich|
|Arijit Banerjee||PhD, 2017||Global Foundries Inc|
|Abhishek Roy||PhD, 2017||Silicon Labs|
|Harsh Patel||PhD, 2017||Global Foundries Inc|
|Divya Akella||PhD, 2017||Mythic Inc|
|He Qi||PhD, 2017||Apple|
|Christopher J. Lukas||PhD, 2017||PsiKick|
|Farah B. Yahya||PhD, 2017||PsiKick|
|Seyi Ayorinde||PhD, 2016||Army Research Lab|
|Manula Pathirana||MS, 2016||Continued for PhD|
|Patricia Gonzalez||MS, 2015||Continued for PhD in EE department at UVA|
|Yu Huang||MS, 2015||Continued for PhD in CS department at UVA|
|Alicia Klinefelter||PhD, 2015||Intel|
|Jim Boley||PhD, 2015||PsiKick|
|Peter Beshay||MS, 2014||Synopsys|
|Kyle Craig||PhD, 2014||PsiKick|
|Aatmesh Shrivastiva||PhD, 2014||PsiKick|
|Craig Eberhardt||PhD, 2013||Envista Forensics|
|Yanqing Zhang||PhD, 2013||Nvidia|
|Yousef Shakhsheer||PhD, 2013||PsiKick|
|Joe Ryan||PhD, 2011||Intel|
|Satyanand Nalam||PhD, 2011||Intel|
|Sudhanshu Khanna||MS, 2011||Texas Instruments|
|Randy Mann||PhD, 2010||GlobalFoundries|
|Jiajing Wang||PhD, 2010||Intel|
|Jonathan Stocking||MS (MAE), 2010||PhD program in Environmental Science, UVA|
|Steven Jocke||MS, 2009||Lockheed Martin|
|Kyle Ringgenberg||MS, 2009||Lockheed Martin|
|Liang Di||MS, 2008||Intel|
|Satyanand Nalam||MS, 2008||continued for PhD|
Year in the Group
|Chuhong Duan||2011-2012||MIT chip testing, Modeling for body sensor nodes; ADESTO chip testing|
|Kevin Linger||2011-2012||Register File Design|
|Vincent Luu||2012||Modeling for Body Sensor, adapting model to COTS|
|Roman Boyarov||2012||Modeling energy efficient COTS embedded systems|
|Ian Dansey||2012||Modeling physiological data|
|David Moore||2010-2012||Interconnect design, multicore processors|
|Andrew Taylor||2012||Standard cell library generation|
|Domenic Carr||2010-2011||CAD for memory design|
|Daniel Reyno||2010-2011||CAD for memory design|
|Tyler Healy||2009||SRAM layout generation|
|Eyad Lababidi||2009||Low voltage FPGA|
|Bijan Mapar||2009||SRAM layout generation|
|Iberedem Ekure||2008||Low voltage FPGA|
|Jisoon Kim||2008||Low voltage FPGA|
|Jay Hoffman||2008||Low power processor|
|Robert McNish||2008||Heart rate processing|
|Daniel Sosa||2008||Traffic control|
|Alex Dreelin||2008||Traffic control|
|Yonathan Habtemichael||2007||Wearable ECG|