Projects

In this paper, we show the first silicon results of a working 512b canary SRAM using reverse assist in 130nm bulk technology which can be tuned to fail earlier than the 8Kb SRAM fails by tuning the bitline or wordline type reverse assists. We further show that this tuning is possible across voltage, frequency, and temperature variations. We report that the 512b canary SRAM has 60% less power consumption than the 8Kb SRAM at 100MHz.
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This work presents an implementation of a 16-bit MSP430 processor for ultra-low-power (ULP) systems catering to battery-less wireless sensor nodes, biomedical, and other IoT applications. Implemented in a custom extremely low power (xLP) 90nm FDSOI process, the processor consumes 1.3μW operating at 0.4V while executing a peak detection algorithm at 250 kHz. It supports the standard MSP430 instruction set architecture (ISA) and...

A 1 trillion node internet of things (IoT) will require sensing platforms that support numerous applications using power harvesting to avoid the cost and scalability challenge of battery replacement in such large numbers. Our previous SoCs achieve good integration and energy harvesting, but they limit supported applications, need higher end-to-end harvesting efficiency, and require duty-cycling for RF communication. In this project, we...

Power supply noise can significantly degrade circuit performance in modern high-performance SoCs. We modeled and explored power supply noise tolerance with a fine-grained globally asynchronous locally synchronous (GALS) design style together with an adaptive clocking scheme. We thank NVIDIA for the collaboration!

This work explores reconfigurable circuits operating at low voltages. While the existing FPGAs are too high power to meet the requirements of IoT applications, we designed and optimized new circuit typologies of CLBs and global interconnect in near/sun-threshold region. We also developed custom tool flow to support full chip configuration. A 90nm chip implements the FPGA with 1134 LUTs, which is 2.7X smaller, 14X faster, and 4.7X less energy than a sub-...

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RLP VLSI

The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. Our group's focus is to confront these problems in a range of applications and different regions of the design space. Our specific research interests include low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and medical applications for low energy electronics. The group is engaged in projects related to each of these topics.