- Chip Gallery
- Photo Gallery
- Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.
- A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications
- Optimizing SRAM Bitcell Reliability and Energy for IoT Applications
- Exploring Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems
- Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications
- A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems
The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. Our group's focus is to confront these problems in a range of applications and different regions of the design space. Our specific research interests include low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and medical applications for low energy electronics. The group is engaged in projects related to each of these topics.