- Self-Powered Systems
- Body Sensor Networks
- Energy Efficient Circuits
- Chip Gallery
- Photo Gallery
- A Tunnel FET Design for High-Current, 120 mV Operation
- An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating
- A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply
- A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic
- Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool
- Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.
The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. Our group's focus is to confront these problems in a range of applications and different regions of the design space. Our specific research interests include low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and medical applications for low energy electronics. The group is engaged in projects related to each of these topics.