Recent Publications
- A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC
- A Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnect
- Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin
- A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs
- Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation
- Energy Efficient Design for Body Sensor Nodes
RLP VLSI
The Robust Low Power VLSI Group, led by Professor Ben Calhoun, investigates research topics related to modern VLSI design. Among the many challenges facing circuit designers in deep sub-micron technologies, power and variation are perhaps the most critical. Our group's focus is to confront these problems in a range of applications and different regions of the design space. Our specific research interests include low power digital circuit design, sub-threshold digital circuits, SRAM design for end-of-the-roadmap silicon, variation tolerant circuit design methodologies, and medical applications for low energy electronics. The group is engaged in projects related to each of these topics.

