Publications
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, “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
, “Design Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
, “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits”, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.
, “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
, “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
, “Device Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
, “A Leakage Reduction Methodology for Distributed MTCMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
, “Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
, “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS”, in European Solid-State Circuits Conference, 2005, pp. 363-366.
, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.
, “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
, “A 256kb Sub-threshold SRAM in 65nm CMOS”, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
, “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, Springer, 2006.
, “Micropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.
, “Power Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, Springer, 2006, pp. 41-75.
, “Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
, “Sub-threshold Design: The Challenges of Minimizing Circuit Energy”, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
, “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
, “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
, “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.
, “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM”, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
, “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
, “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.