Robust Low Power VLSI
VLSI Design Group

Navigation

Search This Site

Publications

Export 45 results:
Author Title Type [ Year(Desc)]
Filters: First Letter Of Last Name is M  [Clear All Filters]
2004
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
2008
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
2009
M. Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
S. Nalam, Bhargava, M., Ringgenberg, K., Mai, K., and Calhoun, B. H., “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
2010
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
S. Nalam, Bhargava, M., Mai, K., and Calhoun, B. H., “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
2011
B. H. Meyer, Calhoun, B. H., Lach, J. C., and Skadron, K., “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy”, CASES. 2011.
C. T. Murphy, W. Eberhardt, C., Calhoun, B. H., and Mann, D. A., “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
C. T. Murphy, W. Eberhardt, C., Calhoun, B. H., and Mann, D. A., “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
R. Mann and Calhoun, B., “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm”, in ISQED, 2011.
R. W. Mann, Hook, T. B., Nguyen, P., and Calhoun, B. H., “Non-Random Device Mismatch Considerations in Nanoscale SRAM”, IEEE Transactions of VLSI Systems (TVLSI), 2011.
B. H. Meyer, Skadron, K., George, N., Calhoun, B. H., and Lach, J., “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.
2012
L. Szafaryn, Chen, J., Calhoun, B. H., Lach, J., Skadron, K., and Meyer, B. H., “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.
2013
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
2014
S. Arrabi, Moore, D., Wang, L., Skadron, K., and Calhoun, B. H., “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems”, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.

Pages