Publications
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Author Title Type [ Year
] Filters: First Letter Of Last Name is G and Author is Shourya Gupta [Clear All Filters]
, “Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2023.
, “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling”, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB), “Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB), “Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB), “MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros”, in IEEE Custom Integrated Circuits Conference (CICC), 2021. kamineni2021.pdf (9.26 MB)
kamineni2021.pdf (9.26 MB), “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB), “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.