Publications
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, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “Micropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.
, “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.
, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design”, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, “A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications”, in Symposium on VLSI Circuits, 2013.
, “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.
, “A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.
, “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
, “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability”, IEEE Solid-State Circuits Letters (SSCL), 2019.
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB), “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.
, “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver”, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
, “A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, IEEE Journal of Solid-State Circuits, 2021.
, “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.
, “A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References”, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.
, “A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References”, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.
, “An Integrated 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μW at 100ms Latency”, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (*Equally-Credited Authors), 2021.