VLSI Design Group

Navigation

Search This Site

Publications

Export 58 results:
Author Title [ Type(Desc)] Year
Filters: First Letter Of Last Name is K  [Clear All Filters]
Conference Paper
A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages, in Symposium on VLSI Circuits, 2014.
X. Liu, Kamineni, S., Breiholz, J., Calhoun, B. H., and Li, S., A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization, in IEEE International Solid-State Circuits Conference (ISSCC), 2022.PDF icon A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB)
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., Chen, X., Wentzloff, D. D., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
X. Chen, Breiholz, J., Yahya, F. B., Lukas, C. J., Kim, H. - S., Calhoun, B. H., and Wentzloff, D. D., A 486 µW All-Digital Bluetooth Low Energy Transmitter with Ring Oscillator Based ADPLL for IoT applications, in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018.
H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic, in European Solid State Circuits Conference (ESSCIRC), 2016.
A. Klinefelter, Roberts, N., Shakhsheer, Y., Gonzalez, P., Shrivastava, A., Roy, A., Craig, K., Faisal, M., Boley, J., Oh, S., Zhang, Y., Akella, D., Wentzloff, D. D., and Calhoun, B., A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios, in ISSCC, San Francisco, CA, 2015.
S. Li, Breiholz, J., Kamineni, S., Im, J., Wentzloff, D. D., and Calhoun, B. H., An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
Y. Shakhsheer, Khanna, S., Craig, K., Arrabi, S., Lach, J., and Calhoun, B. H., A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V, in Custom Integrated Circuits Conference, San Jose, 2011.
J. F. Ryan, Khanna, S., and Calhoun, B. H., An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
S. Kamineni, Sharma, A., Jarjani, R., Sapatnekar, S. S., and Calhoun, B. H., AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells, in Design, Automation and Test in Europe Conference (DATE).
S. Kamineni, Sharma, A., Harjani, R., Sapatnekar, S. S., and Calhoun, B. H., AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells, in Design, Automation and Test in Europe Conference (DATE), 2023, In Press.
F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC, in ISSCC, San Francisco, 2012.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., A battery-less 507nW SoC with integrated platform power manager and SiP interfaces, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
A. Klinefelter, Ryan, J., Tschanz, J., and Calhoun, B. H., Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications, in International Symposium on Circuits and Systems (ISCAS), 2015.
S. Kamineni, Gupta, S., and Calhoun, B. H., MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros, in IEEE Custom Integrated Circuits Conference (CICC), 2021.PDF icon kamineni2021.pdf (9.26 MB)
A. P. Chandrakasan, Verma, N., Kwong, J., Daly, D., Ickes, N., Finchelstein, D., and Calhoun, B. H., Micropower Wireless Sensors, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.
D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks, in ASYNC, 2016.
D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks, in ASYNC, 2016.
D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks, in ASYNC, 2016.
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., An Open-source Framework for Autonomous SoC Design with Analog Block Generation, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., An Open-source Framework for Autonomous SoC Design with Analog Block Generation, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation, in Subthreshold Microelectronics Conference, 2011.
S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
D. Akella Kamakshi, Guo, X., Patel, H. N., Stan, M. R., and Calhoun, B. H., A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
K. Craig, Shakhsheer, Y., Khanna, S., Arrabi, S., Lach, J., Calhoun, B. H., and Kosonocky, S., A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs, in International Symposium on Low Power Electronics and Design, 2012.

Pages