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Author Title [ Type(Desc)] Year
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Book Chapter
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., Low Energy Digital Circuit Design, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., Low Energy Digital Circuit Design, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Design Time – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Standby – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
J. Wang and Calhoun, B. H., Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.
Conference Paper
C. J. Lukas and Calhoun, B. H., A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.
D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability Using a Duty-Cycled Digital Frequency-Locked Loop, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.PDF icon A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
N. Gilbert, Zhang, Y., Dinh, J., Calhoun, B., and Hollmer, S., A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications, in Symposium on VLSI Circuits, 2013.
J. Moody, Dissanayake, A., Bishop, H., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
A. Dissanayake, Moody, J., Bishop, H. L., Truesdell, D. S., Muhlbauer, H., Lu, R., Gao, A., Gong, S., Calhoun, B. H., and Bowers, S. M., A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
A. Shrivastava, Wentzloff, D., and Calhoun, B. H., A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting, in IEEE Custom Integrated Circuits Conference (CICC), 2014.
A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages, in Symposium on VLSI Circuits, 2014.
A. Banerjee, Breiholz, J., and Calhoun, B. H., A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations, in Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015.
A. Roy, Grossmann, P., Vitale, S., and Calhoun, B., A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
Y. Huang, Shrivastava, A., and Calhoun, B. H., A 145mV to 1.2V Single Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.
A. Shrivastava and Calhoun, B. H., A 150nW, 5ppm/oC, 100kHz On-Chip Clock Source for Ultra Low Power SoCs, in Custom Integrated Circuits Conference, San Jose, 2012.
X. Liu, Kamineni, S., Breiholz, J., Calhoun, B. H., and Li, S., A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization, in IEEE International Solid-State Circuits Conference (ISSCC), 2022.PDF icon A 194nW Energy-Performance-Aware IoT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fa.pdf (4.4 MB)
D. Akella, Shrivastava, A., and Calhoun, B. H., A 23 nW CMOS ultra-Low Power Temperature Sensor Operational from 0.2 V, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Rohnert Park, CA, 2015.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
N. E. Roberts, Craig, K., Shrivastava, A., Wooters, S. N., Shakhsheer, Y., Calhoun, B. H., and Wentzloff, D. D., A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.

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