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O. Ayorinde, Qi, H., Huang, Y., and Calhoun, B., “Using island-style bi-directional intra-CLB routing in low-power FPGAs”, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.

H. Qi, Ayorinde, O., and Calhoun, B. H., “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.

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S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.

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J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.

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H. Qi, Ayorinde, O., Huang, Y., and Calhoun, B., “Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs”, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.

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J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “MSN: Memory Sensor for NBTI”, in Techcon, 2009.

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J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.

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O. Ayorinde, Qi, H., and Calhoun, B. H., “FGC: A Tool-flow for Generating and Configuring Custom FPGAs”, Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. ACM, Monterey, CA, 2018.

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H. Qi, Ayorinde, O., and Calhoun, B. H., “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.