Publications
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Author [ Title] Type Year Filters: First Letter Of Last Name is C and Author is B. H. Calhoun [Clear All Filters]
“What is a Body Sensor Network?”, ACM / SIGDA Newsletter, vol. 41, 2011.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT”, in HOT Chips, 2015.
, “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
, “Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors”, in GOMACTech, 2015.
, “A Tunnel FET Design for High-Current, 120 mV Operation”, in IEDM, 2016.
, “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.
, “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
, “A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm”. 2011 Workshop on RFID Security, 2011.
, “Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset”, in International Symposium on Quality Electronic Design, 2015.
, “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
, “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
, “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.
, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
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“Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
, “Non-Random Device Mismatch Considerations in Nanoscale SRAM”, IEEE Transactions of VLSI Systems (TVLSI), 2011.
, “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
, “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
, “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations”, Transactions on VLSI Systems (TVLSI), 2011.
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