Robust Low Power VLSI

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Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 2011.

F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.

L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.

Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.

L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR”, in IEEE Custom Integrated Circuits Conference (CICC), 2023.

Y. Zhang and Calhoun, B. H., “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.

Y. Zhang and Calhoun, B. H., “The Cost of Fixing Hold Time Violations in Sub-threshold Circuits”. 2011.

Y. Zhang and Calhoun, B. H., “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits”, in International Symposium on Quality Electronic Design (ISQED), 2014.