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M. Putic, Di, L., Calhoun, B. H., and Lach, andJohn, Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
H. Patel, Yahya, F., and Calhoun, B., Optimizing SRAM Bitcell Reliability and Energy for IoT Applications, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
H. N. Patel, Mann, R. W., and Calhoun, B. H., Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
H. N. Patel, Yahya, F. B., and Calhoun, B. H., Subthreshold SRAM: Challenges, Design Decisions, and Solutions, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
H. Patel, Yahya, F., and Calhoun, B. H., Improving Reliability and Energy Requirements of Memory in Body Sensor Networks., in International Conference on VLSI Design, Kolkata, India, 2016.
H. N. Patel, Roy, A., Yahya, F. B., Liu, N., Kumeno, K., Yasuda, M., Harada, A., Ema, T., and Calhoun, B. H., A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic, in European Solid State Circuits Conference (ESSCIRC), 2016.