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B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors, in International Symposium on Circuits and Systems, 2009.
B. H. Calhoun and Chandrakasan, A., A 256kb Sub-threshold SRAM in 65nm CMOS, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun and Chandrakasan, A., Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
B. H. Calhoun and Chandrakasan, A., Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS, in European Solid-State Circuits Conference, 2005, pp. 363-366.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
B. H. Calhoun, Ryan, J., Khanna, S., Putic, M., and Lach, J., Flexible Circuits and Architectures for Ultra Low Power, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Device Sizing for Minimum Energy Operation in Subthreshold Circuits, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
B. H. Calhoun, Lach, J., Stankovic, J., Wentzloff, D. D., Whitehouse, K., Barth, A., Brown, J. K., Li, Q., Oh, S., Roberts, N., and Zhang, Y., Body Sensor Networks: A Holistic Approach From Silicon to Users, IEEE Proceedings, 2011.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Standby – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
B. Calhoun and Chandrakasan, A., Standby Voltage Scaling for Reduced Power, in Custom Integrated Circuits Conference (CICC), 2003, pp. 639-642.
B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
B. H. Calhoun, Arrabi, S., Khanna, S., Shakhsheer, Y., Craig, K., Ryan, J., and Lach, J., REESES: Rapid Efficient Energy Scalable ElectronicS, in GOMAC Tech, 2010.
B. H. Calhoun and Chandrakasan, A., Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
B. H. Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic, in GOMAC Tech, 2011.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Design Time – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., Low Energy Digital Circuit Design, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., A Leakage Reduction Methodology for Distributed MTCMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
B. H. Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., Sub-threshold Design: The Challenges of Minimizing Circuit Energy, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
B. H. Calhoun and Lach, J., What is a Body Sensor Network?, ACM / SIGDA Newsletter, vol. 41, 2011.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., Sub-threshold Circuit Design with Shrinking CMOS Devices, in International Symposium on Circuits and Systems, 2009.

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