Publications
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“A 256kb Sub-threshold SRAM in 65nm CMOS”, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
, “Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
, “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS”, in European Solid-State Circuits Conference, 2005, pp. 363-366.
, “Design Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
, “Flexible Circuits and Architectures for Ultra Low Power”, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
, “Device Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
, “Body Sensor Networks: A Holistic Approach From Silicon to Users”, IEEE Proceedings, 2011.
, “Optimizing Power @ Standby – Memory”, in Low Power Design Essentials, 2009.
, “Power Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, Springer, 2006, pp. 41-75.
, “Standby Voltage Scaling for Reduced Power”, in Custom Integrated Circuits Conference (CICC), 2003, pp. 639-642.
, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
, “REESES: Rapid Efficient Energy Scalable ElectronicS”, in GOMAC Tech, 2010.
, “Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.
, “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
, “A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic”, in GOMAC Tech, 2011.
, “Optimizing Power @ Design Time – Memory”, in Low Power Design Essentials, 2009.
, “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, Springer, 2006.
, “A Leakage Reduction Methodology for Distributed MTCMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
, “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms”, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
, “Sub-threshold Design: The Challenges of Minimizing Circuit Energy”, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “What is a Body Sensor Network?”, ACM / SIGDA Newsletter, vol. 41, 2011.
, “Sub-threshold Circuit Design with Shrinking CMOS Devices”, in International Symposium on Circuits and Systems, 2009.
, “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
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