VLSI Design Group

Navigation

Search This Site

Publications

Export 27 results:
[ Author(Desc)] Title Type Year
Filters: First Letter Of Last Name is B  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
B
A. Banerjee and Calhoun, B. H., An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell, in S3S, Monterey, CA, 2013.
A. Banerjee, Sinangil, M., Poulton, J., Gray, C. T., and Calhoun, B. H., A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs, in International Symposium on Quality Electronic Design (ISQED), 2014.
A. Banerjee, A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications, in 32nd International Conference on VLSI Design, 2019.
A. Banerjee and Calhoun, B. H., An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
A. Banerjee, Breiholz, J., and Calhoun, B. H., A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations, in Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015.
A. Banerjee, Kamineni, S., and Calhoun, B. H., Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
A. Banerjee, Liu, N., Patel, H. N., and Calhoun, B. H., A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.
P. Bassirian, Moody, J., Lu, R., Gao, A., Manzaneque, T., Roy, A., N Barker, S., Calhoun, B. H., Gong, S., and Bowers, S. M., Nanowatt-Level Wakeup Receiver Front Ends Using MEMS Resonators for Impedance Transformation, IEEE Transactions on Microwave Theory and Techniques, 2019.
P. Bassirian, Duvvuri, D., Truesdell, D. S., Liu, N. X., Calhoun, B. H., and Bowers, S. M., A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM, in ISLPED, 2014.
P. Beshay, Bolus, J., Blalock, T., Chandra, V., and Calhoun, B. H., SRAM Sense Amplifier Offset Cancellation Using BTI Stress, in Subthreshold Microelectronics Conference, 2012.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM, in Design Automation Conference (DAC), 2014.
P. Beshay, Ryan, J. F., and Calhoun, B. H., A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers, Journal of Low Power Electronics and Applications, 2013.
P. Beshay, Ryan, J. F., and Calhoun, B. H., Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry, in Subthreshold Microelectronics Conference, 2012.
M. Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization, in TECHCON, 2009.
H. L. Bishop, Wang, P., Fan, D., Lach, J., and Calhoun, B. H., Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems, in Global Internet of Things Summit (GIoTS), 2018.
H. L. Bishop, Wang, P., and Calhoun, B. H., Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
H. L. Bishop*, Dissanayake*, A., Bowers, S. M., and Calhoun, B. H., An Integrated 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μW at 100ms Latency, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (*Equally-Credited Authors), 2021.
J. Boley, Calhoun, B. H., and Wang, J., Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin. 2011.
J. Boley, Beshay, P., and Calhoun, B. H., Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization, Transactions of Very Large Scale Integration Systems, 2015.
J. Boley, Wang, J., and Calhoun, B. H., Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.
J. Boley and Calhoun, B. H., Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset, in International Symposium on Quality Electronic Design, 2015.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B., Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN, in Design Automation and Test Europe, 2013.
J. Boley, Wang, J., and Calhoun, B. H., Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin, Journal of Low Power Electronics and Applications, 2012.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., Modeling SRAM Dynamic VMIN, in International Conference on IC Design and Technology (ICICDT), 2014.

Pages