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L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR, in IEEE Custom Integrated Circuits Conference (CICC), 2023.
F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC, in ISSCC, San Francisco, 2012.
Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., Energy Efficient Design for Body Sensor Nodes, Journal of Low Power Electronics and Applications, 2011.
Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
Y. Zhang and Calhoun, B. H., The Cost of Fixing Hold Time Violations in Sub-threshold Circuits. 2011.
Y. Zhang and Calhoun, B. H., Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method, in S3S Conference, Monterey, California, 2013.
Y. Zhang and Calhoun, B. H., Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits, in International Symposium on Quality Electronic Design (ISQED), 2014.
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Y. Yu, Huang, J., Khanna, S., Calhoun, B. H., Lach, J., Shelat, A., and Evans, D., A Sub-0.5V Lattice-Based Public-Key Encryption Scheme for RFID Platforms in 130nm. 2011 Workshop on RFID Security, 2011.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things, Journal of Low Power Electronics & Applications, 2018.
F. Yahya, Patel, H., Boley, J., Banerjee, A., and Calhoun, B. H., A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., A battery-less 507nW SoC with integrated platform power manager and SiP interfaces, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
F. B. Yahya, Lukas, C. J., and Calhoun, B. H., FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
F. B. Yahya, Patel, H. N., Chandra, V., and Calhoun, B. H., Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.
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S. N. Wooters, Calhoun, B. H., and Blalock, T. N., An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., Tracking On-Chip Age Using Distributed, Embedded Sensors, Transactions on VLSI Systems (TVLSI), 2011.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., Tracking On-Chip Age Using Distributed, Embedded Sensors, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes, in International Conference on VLSI Design, 2004, pp. 361-367.
L. Wang, Skadron, K., and Calhoun, B. H., Dark vs. Dim Silicon and Near-Threshold Computing, in Dark Silicon Workshop (DaSi), 2012.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress, in CICC, San Jose, CA, 2010.
J. Wang, Hoefler, A., and Calhoun, B. H., An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction, Transactions on VLSI Systems (TVLSI), 2011.
J. Wang, Nalam, S., and Calhoun, B. H., Analyzing Static and Dynamic Write Margin for Nanometer SRAMs, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., Ultra-Dynamic Voltage Scaling for Energy Starved Electronics, in Proc. of GOMAC Tech, 2007.
J. Wang and Calhoun, B. H., An Enhanced Adaptive Canary System for SRAM Standby Power Reduction, in TECHCON, 2008.
A. Wang and Calhoun, A. Chandrakas, Sub-threshold Design for Ultra Low-Power Systems. Springer, 2006.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.

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