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Conference Paper
A. Banerjee, Breiholz, J., and Calhoun, B. H., A 130nm Canary SRAM for SRAM Dynamic Write VMIN Tracking across Voltage, Frequency, and Temperature Variations, in Custom Integrated Circuits Conference (CICC), San Jose, CA, 2015.
A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages, in Symposium on VLSI Circuits, 2014.
A. Shrivastava, Wentzloff, D., and Calhoun, B. H., A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting, in IEEE Custom Integrated Circuits Conference (CICC), 2014.
A. Dissanayake, Moody, J., Bishop, H. L., Truesdell, D. S., Muhlbauer, H., Lu, R., Gao, A., Gong, S., Calhoun, B. H., and Bowers, S. M., A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
J. Moody, Dissanayake, A., Bishop, H., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR, in IEEE Custom Integrated Circuits Conference (CICC), In Press.
N. Gilbert, Zhang, Y., Dinh, J., Calhoun, B., and Hollmer, S., A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications, in Symposium on VLSI Circuits, 2013.
D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability Using a Duty-Cycled Digital Frequency-Locked Loop, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.PDF icon A 0.5V 560kHz 18.8fJ_Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm_C Stability Using a Duty-Cycled Frequency-Locked Loop.pdf (2.67 MB)
C. J. Lukas and Calhoun, B. H., A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.

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