Robust Low Power VLSI

VLSI Design Group

Search This Site

Publications

Export 258 results:

Author Title [ Type

] Year

Journal Article

J. Moody, Dissanayake, A., Bishop, H. L., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.

R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.

J. Moody, Bassirian, P., Roy, A., Liu, N. X., N Barker, S., Calhoun, B. H., and Bowers, S. M., “Interference Robust Detector-First Near-Zero Power Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2019.

B. H. Calhoun, Honore, F. A., and Chandrakasan, A., “A Leakage Reduction Methodology for Distributed MTCMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.

J. Wang and Calhoun, B. H., “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations”, Transactions on VLSI Systems (TVLSI), 2011.

D. S. Truesdell, Ahmed, S. Z., Ghosh, A. W., and Calhoun, B. H., “Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.

Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)

B. H. Calhoun, Wang, A., and Chandrakasan, A., “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.

S. Z. Ahmed, Tan, Y., Truesdell, D. S., Calhoun, B. H., and Ghosh, A., “Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance”, Journal of Applied Physics, 2018.

P. Bassirian, Moody, J., Lu, R., Gao, A., Manzaneque, T., Roy, A., N Barker, S., Calhoun, B. H., Gong, S., and Bowers, S. M., “Nanowatt-Level Wakeup Receiver Front Ends Using MEMS Resonators for Impedance Transformation”, IEEE Transactions on Microwave Theory and Techniques, 2019.

R. W. Mann, Hook, T. B., Nguyen, P., and Calhoun, B. H., “Non-Random Device Mismatch Considerations in Nanoscale SRAM”, IEEE Transactions of VLSI Systems (TVLSI), 2011.

S. Li, Roy, A., and Calhoun, B. H., “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated Maximum-Power-Point Tracking”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.

A. Klinefelter, Zhang, Y., Otis, B., and Calhoun, B. H., “A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, p. 941, 2012.

D. S. Truesdell and Calhoun, B. H., “A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range”, IEEE Solid-State Circuits Letters (SSCL), 2020.

A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)

B. H. Calhoun and Chandrakasan, A., “Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.

B. H. Calhoun and Chandrakasan, A., “Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.

X. Liu, Calhoun, B. H., and Li, S., “A Sub-nW 93% Peak Efficiency Buck Converter with Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control”, IEEE Journal of Solid-State Circuits, (invited paper), 2022.

A SubnW 93 Peak Efficiency Buck Converter With Wide Dynamic Range Fast DVFS and Asynchronous Load Transient Control.pdf (3.94 MB)

F. Yahya, Patel, H., Boley, J., Banerjee, A., and Calhoun, B. H., “A Sub-threshold 8T SRAM Macro with 12.29nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

X. Liu, Kamineni, S., Breiholz, J., Calhoun, B. H., and Li, S., “A Sub-µW Energy-Performance-Aware IoT SoC with a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization”, IEEE Journal of Solid-State Circuits, 2024.

A_Sub-_mu_W_Energy-Performance-Aware_IoT_SoC_With_a_Triple_Mode_Power_Management_Unit_for_System_Performance_Scaling_Fast_DVFS_and_Energy_Minimization.pdf (7.38 MB)

J. Wang and Calhoun, B. H., “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.

F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things”, Journal of Low Power Electronics & Applications, 2018.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.

S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.

J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.

B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.

A. Banerjee and Calhoun, B. H., “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.

Pages