VLSI Design Group

Navigation

Search This Site

Publications

Export 323 results:
Author [ Title(Asc)] Type Year
Filters: First Letter Of Last Name is C  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
A
S. Kamineni, Sharma, A., Harjani, R., Sapatnekar, S. S., and Calhoun, B. H., AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells, in Design, Automation and Test in Europe Conference (DATE), 2023, 2023.PDF icon AuxcellGen-A Framework for Autonomous Generation of Analog and Memory Unit Cells.pdf (3.37 MB)
S. Nalam and Calhoun, B. H., Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T, in CICC, 2009, pp. 709-712.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation, in ISQED, 2010, pp. 139-146.
S. Nalam, Chandra, V., Pietrzyk, C., Aitken, R. C., and Calhoun, B. H., Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation, in ISQED, 2010, pp. 139-146.
H. L. Bishop, Wang, P., and Calhoun, B. H., Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
J. Boley, Wang, J., and Calhoun, B. H., Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin, Journal of Low Power Electronics and Applications, 2012.
J. Boley, Wang, J., and Calhoun, B. H., Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.
J. Boley, Calhoun, B. H., and Wang, J., Analyzing Subthreshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin. 2011.
B. H. Calhoun and Chandrakasan, A., Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS, in European Solid-State Circuits Conference, 2005, pp. 363-366.
B. H. Calhoun and Chandrakasan, A., Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS, in European Solid-State Circuits Conference, 2005, pp. 363-366.
J. Wang, Nalam, S., and Calhoun, B. H., Analyzing Static and Dynamic Write Margin for Nanometer SRAMs, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
J. F. Ryan, Wang, J., and Calhoun, B. H., Analyzing and Modeling Process Balance for Sub-threshold Circuit Design, in GLSVLSI, 2007, pp. 275-280.
J. F. Ryan, Khanna, S., and Calhoun, B. H., An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
X. Chen, Breiholz, J., Yahya, F. B., Lukas, C. J., Kim, H. - S., Calhoun, B. H., and Wentzloff, D. D., Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 Frequency Edge Combiner, IEEE Journal of Solid-State Circuits, 2019.
X. Chen, Breiholz, J., Yahya, F. B., Lukas, C. J., Kim, H. - S., Calhoun, B. H., and Wentzloff, D. D., Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 Frequency Edge Combiner, IEEE Journal of Solid-State Circuits, 2019.
8
R. Agarwala, Wang, P., Tanneeru, A., Lee, B., Misra, V., and Calhoun, B. H., An 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Range, in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.
S. Li, Breiholz, J., Kamineni, S., Im, J., Wentzloff, D. D., and Calhoun, B. H., An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
J. Moody, Bassirian, P., Roy, A., Feng, Y., Li, S., Costanzo, R., N. Barker, S., Calhoun, B. H., and Bowers, S. M., An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
X. Liu, Li, S., and Calhoun, B. H., An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control, in 2021 IEEE European Solid-State Circuits Conference (ESSCIRC), 2021.PDF icon An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control.pdf (580.42 KB)

Pages