Publications
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Author [ Title] Type Year Filters: First Letter Of Last Name is C [Clear All Filters]
“Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation”, in International Symposium on Low Power Electronics and Design, 2012.
, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.
, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.
, “Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs”, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.
, “Optimizing Power @ Design Time – Memory”, in Low Power Design Essentials, 2009.
, “Optimizing Power @ Standby – Memory”, in Low Power Design Essentials, 2009.
, “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design”, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated Maximum-Power-Point Tracking”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
, “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
, “Power Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, Springer, 2006, pp. 41-75.
, “Power Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, Springer, 2006, pp. 41-75.
, “Power Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, Springer, 2006, pp. 41-75.
, “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.
, “A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, p. 941, 2012.
, , “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.
, “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
, “Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy”, in SRC Techcon, 2012.
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