VLSI Design Group

Navigation

Search This Site

Publications

Export 159 results:
Author [ Title(Desc)] Type Year
Filters: First Letter Of Last Name is C and Author is Benton H. Calhoun  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
T
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.
U
A. Banerjee and Calhoun, B. H., An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell, in S3S, Monterey, CA, 2013.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., Ultra-Dynamic Voltage Scaling for Energy Starved Electronics, in Proc. of GOMAC Tech, 2007.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Ultra-Low-Power FPGA for IoT Applications, in S3S 2017, 2017.
A. Mallick, Bashar, M. K., Truesdell, D. S., Calhoun, B. H., Joshi, S., and Shukla, N., Using synchronized oscillators to compute the maximum independent set, Nature Communications, 2020.

Pages