Publications
] , “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
, “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.
, “Application-Driven Model of a PPG Sensing Modality for the Informed Design of Self-Powered, Wearable Healthcare Systems”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
, “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.
, “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN”, Journal of Low Power Electronics and Applications (JLPEA), vol. 2, p. 12, 2012.
, “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS”, in European Solid-State Circuits Conference, 2005, pp. 363-366.
, “Analyzing Static and Dynamic Write Margin for Nanometer SRAMs”, in International Symposium on Low Power Electronics and Design, 2008, pp. 129-134.
, “Analyzing and Modeling Process Balance for Sub-threshold Circuit Design”, in GLSVLSI, 2007, pp. 275-280.
, “An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, in Internation Symposium on Lower Power Electronics and Design (ISLPED), 2011.
, “Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 Frequency Edge Combiner”, IEEE Journal of Solid-State Circuits, 2019.
, “A 956pW Switched-Capacitor Sub-Bandgap Reference with 0.44-to-3.3V Supply Range, -67dB PSRR, and 0.2% within-Wafer Inaccuracy for Nanowatt IoT Systems”, in 2022 IEEE European Solid-State Circuits Conference (ESSCIRC), 2022.
, “A 90nm Data Flow Processor Demonstrating Fine Grained DVS for Energy Efficient Operation from 0.25V to 1.2V”, in Custom Integrated Circuits Conference, San Jose, 2011.
, “An 88.6nW Ozone Pollutant Sensing Interface IC with a 159 dB Dynamic Range”, in ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2020.
, “An 85 nW IoT Node-Controlling SoC for MELs Power-Mode Management and Phantom Energy Reduction”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
, “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
, “An 81.0% Peak Efficiency, 1.0W/cm^3 Miniaturized 5V/1A AC-DC Converter using a Highly-Integrated Primary-Side Active Clamp Flyback Controller with Adaptive Frequency and Zero-Voltage Switching”, in 2025 IEEE Custom Integrated Circuits Conference (CICC), In Press.
, “An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control”, in 2021 IEEE European Solid-State Circuits Conference (ESSCIRC), 2021.
An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control.pdf (580.42 KB)
An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control.pdf (580.42 KB), “A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, “A -76dBm 7.4 nW wakeup radio with automatic offset compensation”, in International Solid-State Circuits Conference (ISSCC), 2018.
, “A 745pA Hybrid Asynchronous Binary-Searching and Synchronous Linear-Searching Digital LDO with 3.8×105 Dynamic Load Range, 99.99% Current Efficiency, and 2mV Output Voltage Ripple”, in IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, 2019.
, “A 71% Efficient Energy Harvesting and Power Management Unit for Sub-µW Power Biomedical Applications”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
, “A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic”, IEEE Solid-State Circuits Letters (SSCL), 2019. A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB), “A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output Power Management System with Multi-Rail Energy Sharing, All-Rail Cold Startup, and Adaptive Conversion Control for mm-scale Distributed Systems”, in 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024. A_6nA_Fully Autonomous_Triple-Input_Hybrid-Inductor-Capacitor_Multi-Output_Power_Management_System_with_Multi-Rail_Energy_Sharing_All-Rail_Cold_Startup_and_Adaptive_Conve.pdf (1.55 MB)
A_6nA_Fully Autonomous_Triple-Input_Hybrid-Inductor-Capacitor_Multi-Output_Power_Management_System_with_Multi-Rail_Energy_Sharing_All-Rail_Cold_Startup_and_Adaptive_Conve.pdf (1.55 MB), “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020. A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)