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S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
D. Akella Kamakshi, Guo, X., Patel, H. N., Stan, M. R., and Calhoun, B. H., A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
L. Di, Putic, M., Lach, J., and Calhoun, B. H., Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling, in International Conference on Computer Design, pages 605-611, 2008.
A. Klinefelter, Zhang, Y., Otis, B., and Calhoun, B. H., A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, p. 941, 2012.
A. M. Klinefelter and Calhoun, B. H., A Programmable Multi-channel Sub-threshold FIR Filter for a Body Area Sensor Node. 2011.
K. Craig, Shakhsheer, Y., Khanna, S., Arrabi, S., Lach, J., Calhoun, B. H., and Kosonocky, S., A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs, in International Symposium on Low Power Electronics and Design, 2012.
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P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM, in Design Automation Conference (DAC), 2014.
X. Liu, Truesdell, D. S., Faruqe, O., Parameswaran, L., Rickley, M., Kopanski, A., Cantley, L., Coon, A., Bernasconi, M., Wang, T., and Calhoun, B. H., A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber, in IEEE International Solid-State Circuits Conference (ISSCC), In Press.
S. Khanna and Calhoun, B. H., Serial Sub-threshold Circuits for Ultra-Low-Power Systems, in International Symposium on Low Power Electronics and Design, 2009.
D. S. Truesdell and Calhoun, B. H., A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ/Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range, IEEE Solid-State Circuits Letters (SSCL), 2020.PDF icon A Single-Supply 6-Transistor Voltage Level Converter Design Reaching 8.18-fJ_Transition at 0.3-1.2-V Range or 44-fW Leakage at 0.8-2.5-V Range.pdf (1.06 MB)
H. N. Patel, Mann, R. W., and Calhoun, B. H., Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
M. Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization, in TECHCON, 2009.
P. Beshay, Bolus, J., Blalock, T., Chandra, V., and Calhoun, B. H., SRAM Sense Amplifier Offset Cancellation Using BTI Stress, in Subthreshold Microelectronics Conference, 2012.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., SRAM-Based NBTI/PBTI Sensor System Design, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
J. Boley and Calhoun, B. H., Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset, in International Symposium on Quality Electronic Design, 2015.
A. Dissanayake, Bowers, S. M., and Calhoun, B. H., Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
B. H. Calhoun and Chandrakasan, A., Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.
J. Wang and Calhoun, B. H., Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.

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