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S. Gupta and Calhoun, B. H., Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
A. Banerjee, A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications, in 32nd International Conference on VLSI Design, 2019.
X. Liu, Agrawal, A., Tanaka, A., and Calhoun, B. H., Distributed Energy Harvesting and Power Management Units for Self-Powered In-Fabric Sensing Networks, 2024 IEEE Midwest Symposium on Circuits and Systems (MWSCAS), invited paper, 2024.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM, in ISLPED, 2014.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM, in ISLPED, 2014.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
P. Beshay, Ryan, J. F., and Calhoun, B. H., A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers, Journal of Low Power Electronics and Applications, 2013.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Device Sizing for Minimum Energy Operation in Subthreshold Circuits, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Device Sizing for Minimum Energy Operation in Subthreshold Circuits, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
W. Eberhardt, Wakefield, B., Casey, C., Murphy, C., Calhoun, B. H., and Reichmuth, C., Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array, Bioinspiration and Biomimetics, 2016.
W. Eberhardt, Wakefield, B., Casey, C., Murphy, C., Calhoun, B. H., and Reichmuth, C., Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array, Bioinspiration and Biomimetics, 2016.
B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
N. Liu and Calhoun, B. H., Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes, in International Conference on VLSI Design, 2004, pp. 361-367.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes, in International Conference on VLSI Design, 2004, pp. 361-367.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
Y. Huang, Shrivastava, A., Barnes, L., and Calhoun, B. H., A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

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