Publications
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, “Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB), “A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications”, in 32nd International Conference on VLSI Design, 2019.
, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
, “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.
, “Device Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
, “Device Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
, “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
, “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
, “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
, “Design Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
, “Design Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
, “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
, “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
, “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
, “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
, “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.