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Y. Zhang and Calhoun, B. H., “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.

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R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., “Impact of circuit assist methods on margin and performance in 6T SRAM”, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.

D. S. Truesdell and Calhoun, B. H., “Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.

H. Patel, Yahya, F., and Calhoun, B. H., “Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.”, in International Conference on VLSI Design, Kolkata, India, 2016.

J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.

H. L. Bishop*, Dissanayake*, A., Bowers, S. M., and Calhoun, B. H., “An Integrated 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μW at 100ms Latency”, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (*Equally-Credited Authors), 2021.

J. Moody, Bassirian, P., Roy, A., Liu, N. X., N Barker, S., Calhoun, B. H., and Bowers, S. M., “Interference Robust Detector-First Near-Zero Power Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2019.

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B. H. Calhoun, Honore, F. A., and Chandrakasan, A., “A Leakage Reduction Methodology for Distributed MTCMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.

B. H. Calhoun, Honore, F. A., and Chandrakasan, A., “A Leakage Reduction Methodology for Distributed MTCMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.

J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.

J. Boley, Chandra, V., Aitken, R., and Calhoun, B., “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.

J. Boley, Chandra, V., Aitken, R., and Calhoun, B., “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.

H. L. Bishop, Wang, P., Fan, D., Lach, J., and Calhoun, B. H., “Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems”, in Global Internet of Things Summit (GIoTS), 2018.

B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.

B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.

O. Abdelatty, Bishop, H., Shi, Y., Chen, X., Alghaihab, A., Calhoun, B., and Wentzloff, D., “A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Cracow, Poland, 2019.

O. Abdelatty, Bishop, H., Shi, Y., Chen, X., Alghaihab, A., Calhoun, B., and Wentzloff, D., “A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Cracow, Poland, 2019.

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S. Kamineni, Gupta, S., and Calhoun, B. H., “MemGen: An Open-Source Framework for Autonomous Generation of Memory Macros”, in IEEE Custom Integrated Circuits Conference (CICC), 2021.

kamineni2021.pdf (9.26 MB)

A. P. Chandrakasan, Verma, N., Kwong, J., Daly, D., Ickes, N., Finchelstein, D., and Calhoun, B. H., “Micropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.

A. P. Chandrakasan, Verma, N., Kwong, J., Daly, D., Ickes, N., Finchelstein, D., and Calhoun, B. H., “Micropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.

J. F. Ryan and Calhoun, B. H., “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation”, in International Symposium on Quality Electronic Design, 2008, pp. 127-132.

J. Wang and Calhoun, B. H., “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations”, Transactions on VLSI Systems (TVLSI), 2011.

D. S. Truesdell, Ahmed, S. Z., Ghosh, A. W., and Calhoun, B. H., “Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.

Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)

A. D. Jurik, Bolus, J., Weaver, A. F., Calhoun, B. H., and Blalock., T. N., “Mobile Health Monitoring Through Biotelemetry”, in Bodynets, 2009.

D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.

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