Publications
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, “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
, “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.
, “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.
, “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.
, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting”, in IEEE Custom Integrated Circuits Conference (CICC), 2014.
, “A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages”, in Symposium on VLSI Circuits, 2014.
, “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.
, “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.
, “39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 16, 2014.
, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems”, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
, “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.
, “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
, “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
, “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
, “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
, “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
, “A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems”, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.