Robust Low Power VLSI
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Conference Paper
C. J. Lukas and Calhoun, B. H., “A 0.38 pJ/bit 1.24 nW Chip-to-Chip Serial Link for Ultra-Low Power Systems”, in International Symposium on Circuits and Systems (ISCAS), Lisbon, 2015.
Book Chapter
J. Wang and Calhoun, B. H., “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.
B. H. Calhoun, ,, and Chandrakasan, A., “Power Gating and Dynamic Voltage Scaling”, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
B. H. Calhoun and Rabaey, J., “Optimizing Power @ Standby – Memory”, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun and Rabaey, J., “Optimizing Power @ Design Time – Memory”, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., “Low Energy Digital Circuit Design”, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
Book
B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.

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