VLSI Design Group

Navigation

Search This Site

Publications

Conference Paper
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
B. H. Calhoun and Wentzloff, D. D., Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT, in HOT Chips, 2015.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Ultra-Low-Power FPGA for IoT Applications, in S3S 2017, 2017.
O. Ayorinde, Qi, H., Huang, Y., and Calhoun, B., Using island-style bi-directional intra-CLB routing in low-power FPGAs, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.
S. Nalam, Bhargava, M., Mai, K., and Calhoun, B. H., Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers, in Design Automation Conference (DAC), 2010, pp. 138-143.
J. Boley, Beshay, P., and Calhoun, B., Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization, in SRC TECHCON, 2013.
Journal Article
A. D. Kamakshi, Shrivastava, A., and Calhoun, B. H., A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
A. Kosari, Breiholz, J., Liu, N. X., Calhoun, B. H., and Wentzloff, D. D., A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis, Journal of Low Power Electronics and Applications (JLPEA), 2018.
D. S. Truesdell, Li, S., and Calhoun, B. H., A 0.5V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator with 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop, IEEE Journal of Solid-State Circuits, 2021.PDF icon A 0.5-V 560-kHz 18.8-fJ_Cycle On-Chip Oscillator With 96.1ppm_C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop.pdf (2.95 MB)
D. S. Truesdell, Dissanayake, A., and Calhoun, B. H., A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)
R. Agarwala, Wang, P., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring, IEEE Journal of Solid-State Circuits, 2021.
C. J. Lukas, Yahya, F. B., Breiholz, J., Roy, A., Chen, X., Patel, H. N., Liu, N. X., Kosari, A., Li, S., Kamakshi, D. Akella, Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications, IEEE Transactions on Biomedical Circuits and Systems, 2019.PDF icon 08625544.pdf (3.22 MB)
A. Shrivastava, Roberts, N. E., Khan, O. U., Wentzloff, D. D., and Calhoun, B. H., A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting with 220mV Cold-Start and -14.5dBm, 915MHz RF Kick-Start, IEEE Journal of Solid-State Circuits (JSSC), vol. 50, pp. 1820-1832, 2015.
A. Shrivastava, Akella, D., and Calhoun, B. H., A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.
X. Shen, Duvvuri, D., Bassirian, P., Bishop, H. L., Liu, X., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., A 184 nW, -78.3 dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-up Receiver at 4.9 GHz, IEEE Transactions on Microwave Theory and Techniques, 2022.
A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver, IEEE Journal of Solid-State Circuits, 2021.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time, IEEE Journal of Solid-State Circuits (JSSC), 2019.
B. H. Calhoun and Chandrakasan, A., A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance, Journal of Solid State Circuits, 2014.

Pages