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Conference Paper
P. Beshay, Ryan, J. F., and Calhoun, B. H., Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry, in Subthreshold Microelectronics Conference, 2012.
H. N. Patel, Yahya, F. B., and Calhoun, B. H., Subthreshold SRAM: Challenges, Design Decisions, and Solutions, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
B. H. Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
S. Nalam, Bhargava, M., Ringgenberg, K., Mai, K., and Calhoun, B. H., A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes, in ICCD, 2009, pp. 523-528.
P. Bassirian, Duvvuri, D., Truesdell, D. S., Liu, N. X., Calhoun, B. H., and Bowers, S. M., A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
P. Long, Huang, J. Z., Povolotskyi, M., Verreck, D., Charles, J., Kubis, T., Klimeck, G., Rodwell, M. J. W., and Calhoun, B. H., A Tunnel FET Design for High-Current, 120 mV Operation, in IEDM, 2016.
A. Banerjee and Calhoun, B. H., An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell, in S3S, Monterey, CA, 2013.
Y. Shakhsheer, Shrivastava, A., Roberts, N., Craig, K., Wooters, S., Wentzloff, D. D., and Calhoun, B. H., Ultra Low Power Circuits and Systems for Self Powered Wireless Sensors, in GOMACTech, 2015.
A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., Ultra-Dynamic Voltage Scaling for Energy Starved Electronics, in Proc. of GOMAC Tech, 2007.
B. H. Calhoun and Chandrakasan, A., Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
B. H. Calhoun and Wentzloff, D. D., Ultra-Low Power Wireless SoCs Enabling a Batteryless IoT, in HOT Chips, 2015.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Ultra-Low-Power FPGA for IoT Applications, in S3S 2017, 2017.
O. Ayorinde, Qi, H., Huang, Y., and Calhoun, B., Using island-style bi-directional intra-CLB routing in low-power FPGAs, in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015.
S. Nalam, Bhargava, M., Mai, K., and Calhoun, B. H., Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers, in Design Automation Conference (DAC), 2010, pp. 138-143.
J. Boley, Beshay, P., and Calhoun, B., Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization, in SRC TECHCON, 2013.