Publications
Export 336 results:
Author Title [ Type
] Year Filters: First Letter Of Last Name is C [Clear All Filters]
, “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
, “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems”, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
, “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
, “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
, “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling”, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB), “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm”, in ISQED, 2011.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation”, in International Symposium on Low Power Electronics and Design, 2012.
, “Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation”, in International Symposium on Low Power Electronics and Design, 2012.
, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.
, “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.
, “Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs”, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.
, “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design”, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, “A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
, “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
, “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.
, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.
, “Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design”, in International Conference on VLSI Design, India, 2008, pp. 131-136.
, “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication”, in Design Automation and Test in Europe (DATE), 2011.