VLSI Design Group

Navigation

Search This Site

Publications

Export 236 results:
Author [ Title(Desc)] Type Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
M
K. Flynn, Ownby, N., Wang, P., and Calhoun, B. H., Modeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypes, in IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., Modeling SRAM Dynamic VMIN, in International Conference on IC Design and Technology (ICICDT), 2014.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
S. Z. Ahmed, Tan, Y., Truesdell, D. S., Calhoun, B. H., and Ghosh, A., Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance, Journal of Applied Physics, 2018.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., MSN: Memory Sensor for NBTI, in Techcon, 2009.
A. Dissanayake, Bishop, H. L., Moody, J., Muhlbauer, H., Calhoun, B. H., and Bowers, S. M., A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
A. Banerjee, Kamineni, S., and Calhoun, B. H., Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
O
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., An Open-source Framework for Autonomous SoC Design with Analog Block Generation, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
K. Craig, Shakhsheer, Y., and Calhoun, B. H., Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation, in International Symposium on Low Power Electronics and Design, 2012.
K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation, in Subthreshold Microelectronics Conference, 2011.
H. Qi, Ayorinde, O., Huang, Y., and Calhoun, B., Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Design Time – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
B. H. Calhoun and Rabaey, J., Optimizing Power @ Standby – Memory, in Low Power Design Essentials, J. Rabaey, Ed. 2009.
H. Patel, Yahya, F., and Calhoun, B., Optimizing SRAM Bitcell Reliability and Energy for IoT Applications, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
P
M. Putic, Di, L., Calhoun, B. H., and Lach, andJohn, Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
S. Li, Roy, A., and Calhoun, B. H., A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
S. Li, Roy, A., and Calhoun, B. H., A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated Maximum-Power-Point Tracking, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
D. Akella Kamakshi, Guo, X., Patel, H. N., Stan, M. R., and Calhoun, B. H., A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
B. H. Calhoun, ,, and Chandrakasan, A., Power Gating and Dynamic Voltage Scaling, in Leakage in Nanometer Technologies, S. Narendra and Chandrakasan, A., Eds. Springer, 2006, pp. 41-75.
L. Di, Putic, M., Lach, J., and Calhoun, B. H., Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling, in International Conference on Computer Design, pages 605-611, 2008.

Pages