Robust Low Power VLSI

VLSI Design Group

Search This Site

Publications

Export 259 results:

] Title Type Year

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

H

Y. Huang, Shrivastava, A., Barnes, L., and Calhoun, B. H., “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.

M. A. Hanson, Jr, H. C. Powell, Barth, A. T., Ringgenberg, K., Calhoun, B. H., Aylor, J. H., and Lach, J., “Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.

G

S. Gupta, Li, S., and Calhoun, B. H., “Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS”, in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, 2023.

S. Gupta, Truesdell, D. S., and Calhoun, B. H., “A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.

A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)

S. Gupta and Calhoun, B. H., “Dynamic Read V_MIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.

Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)

S. Gupta and Calhoun, B. H., “Dynamic Write V_MIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.

Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)

M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.

J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.

N. Gilbert, Zhang, Y., Dinh, J., Calhoun, B., and Hollmer, S., “A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications”, in Symposium on VLSI Circuits, 2013.

F

K. Flynn, Ownby, N., Wang, P., and Calhoun, B. H., “Modeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypes”, in IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021.

O. Faruqe, Chen, Z., Bhattacharya, S., Foysal, M. Fahim, Hasan, S., Truesdell, D. S., and Calhoun, B. H., “A 0.36 mm² On-the-Fly I2C-to-SPI Converter for E-Textile Applications”, in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), In Press.

O. Faruqe, Lee, D., Ownby, N., and Calhoun, B. H., “A 10-Channel, 1.2 µW, Reconfigurable Capacitanceto-Digital Converter for Low-Power, Wearable Healthcare Applications”, in 2023 IEEE Biomedical Circuits and Systems Conference, 2023.

O. Faruqe, Le, P., Lee, D., Liu, X., Abdelatty, O., Truesdell, D. S., and Calhoun, B. H., “A Fully Integrated, Custom End-to-End PPG Sensing System for Ultra-Low Power Wearables”, in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), In Press.

O. Faruqe, Lee, D., Ownby, N., and Calhoun, B. H., “A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-μW Robust Wearable Sensing”, IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 4, 2024.

E

W. C. Eberhardt, Shakhsheer, Y. A., and Calhoun, B. H., “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability”, in IEEE Sensors, Limrick, Ireland, 2011.

W. Eberhardt, Wakefield, B., Casey, C., Murphy, C., Calhoun, B. H., and Reichmuth, C., “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.

D

D. Duvvuri, Shen, X., Bassirian, P., Bishop, H. L., Liu, X., Chen, C. - H., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References”, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.

A. Dissanayake, Bishop, H. L., Moody, J., Muhlbauer, H., Calhoun, B. H., and Bowers, S. M., “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.

A. Dissanayake, Moody, J., Bishop, H. L., Truesdell, D. S., Muhlbauer, H., Lu, R., Gao, A., Gong, S., Calhoun, B. H., and Bowers, S. M., “A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver”, in IEEE Custom Integrated Circuits Conference (CICC), 2020.

A. Dissanayake, Bowers, S. M., and Calhoun, B. H., “Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.

A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.

L. Di, Putic, M., Lach, J., and Calhoun, B. H., “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.

C

K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.

K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.

K. Craig, Shakhsheer, Y., Khanna, S., Arrabi, S., Lach, J., Calhoun, B. H., and Kosonocky, S., “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.

Pages