Robust Low Power VLSI

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E

W. C. Eberhardt, Shakhsheer, Y. A., and Calhoun, B. H., “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability”, in IEEE Sensors, Limrick, Ireland, 2011.

D

D. Duvvuri, Shen, X., Bassirian, P., Bishop, H. L., Liu, X., Chen, C. - H., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References”, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.

A. Dissanayake, Bowers, S. M., and Calhoun, B. H., “Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.

A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.

A. Dissanayake, Bishop, H. L., Moody, J., Muhlbauer, H., Calhoun, B. H., and Bowers, S. M., “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.

A. Dissanayake, Moody, J., Bishop, H. L., Truesdell, D. S., Muhlbauer, H., Lu, R., Gao, A., Gong, S., Calhoun, B. H., and Bowers, S. M., “A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver”, in IEEE Custom Integrated Circuits Conference (CICC), 2020.

L. Di, Putic, M., Lach, J., and Calhoun, B. H., “Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling”, in International Conference on Computer Design, pages 605-611, 2008.

C

K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., “Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation”, in Subthreshold Microelectronics Conference, 2011.

K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.

K. Craig, Shakhsheer, Y., Khanna, S., Arrabi, S., Lach, J., Calhoun, B. H., and Kosonocky, S., “A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs”, in International Symposium on Low Power Electronics and Design, 2012.

K. Craig, Shakhsheer, Y., and Calhoun, B. H., “Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation”, in International Symposium on Low Power Electronics and Design, 2012.

X. Chen, Breiholz, J., Yahya, F. B., Lukas, C. J., Kim, H. - S., Calhoun, B. H., and Wentzloff, D. D., “Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 Frequency Edge Combiner”, IEEE Journal of Solid-State Circuits, 2019.

X. Chen, Breiholz, J., Yahya, F. B., Lukas, C. J., Kim, H. - S., Calhoun, B. H., and Wentzloff, D. D., “A 486 µW All-Digital Bluetooth Low Energy Transmitter with Ring Oscillator Based ADPLL for IoT applications”, in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2018.

X. Chen, Alghaihab, A., Shi, Y., Truesdell, D. S., Calhoun, B. H., and Wentzloff, D. D., “A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets”, IEEE Journal of Solid-State Circuits, 2021.

A. P. Chandrakasan, Verma, N., Kwong, J., Daly, D., Ickes, N., Finchelstein, D., and Calhoun, B. H., “Micropower Wireless Sensors”, in NSTI Nanotech, 2006, vol. 3, pp. 459-462.

B. H. Calhoun, Wang, A., and Chandrakasan, A., “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.

B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.

B. H. Calhoun and Rabaey, J., “Optimizing Power @ Design Time – Memory”, in Low Power Design Essentials, J. Rabaey, Ed. 2009.

B. Calhoun and Chandrakasan, A., “Standby Voltage Scaling for Reduced Power”, in Custom Integrated Circuits Conference (CICC), 2003, pp. 639-642.

B. H. Calhoun and Chandrakasan, A., “A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation”, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.

B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.

B. H. Calhoun and Chandrakasan, A., “Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.

B. H. Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms”, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.

B. H. Calhoun and Chandrakasan, A., “Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS”, in European Solid-State Circuits Conference, 2005, pp. 363-366.

B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.

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