Publications
] , “A -76dBm 7.4 nW wakeup radio with automatic offset compensation”, in International Solid-State Circuits Conference (ISSCC), 2018.
, “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
, “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
, “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
, “Interference Robust Detector-First Near-Zero Power Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2019.
, “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
, “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “5T SRAM with Asymmetric Sizing for Improved Read Stability”, JSSC, 2011.
, “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
, “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM”, in Design Automation and Test Europe (DATE), 2011.
, “Modeling Energy Aware Photoplethsmography for Personalized Healthcare Applications”, in IEEE Transactions on Biomedical Circuits and Systems, 2022.
, “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.
, “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
, “Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.”, in International Conference on VLSI Design, Kolkata, India, 2016.
, “Optimizing SRAM Bitcell Reliability and Energy for IoT Applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, “Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications”, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
, “Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design”, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
, “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
, “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
, “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
, “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
, “Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs”, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.