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Conference Paper
A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design, in International Conference on VLSI Design, India, 2008, pp. 131-136.
A. Klinefelter and Calhoun, B. H., A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs, in S3S Conference, Monterey, CA, 2014.
B. H. Meyer, Skadron, K., George, N., Calhoun, B. H., and Lach, J., Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication, in Design Automation and Test in Europe (DATE), 2011.
L. Szafaryn, Chen, J., Calhoun, B. H., Lach, J., Skadron, K., and Meyer, B. H., Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy, in SRC Techcon, 2012.
B. H. Calhoun, Arrabi, S., Khanna, S., Shakhsheer, Y., Craig, K., Ryan, J., and Lach, J., REESES: Rapid Efficient Energy Scalable ElectronicS, in GOMAC Tech, 2010.
A. Banerjee, Sinangil, M., Poulton, J., Gray, C. T., and Calhoun, B. H., A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs, in International Symposium on Quality Electronic Design (ISQED), 2014.
S. Gupta, Li, S., and Calhoun, B. H., Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM, in Design Automation Conference (DAC), 2014.
X. Liu, Truesdell, D. S., Faruqe, O., Parameswaran, L., Rickley, M., Kopanski, A., Cantley, L., Coon, A., Bernasconi, M., Wang, T., and Calhoun, B. H., A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber, in IEEE International Solid-State Circuits Conference (ISSCC), 2023.PDF icon 15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB)
S. Khanna and Calhoun, B. H., Serial Sub-threshold Circuits for Ultra-Low-Power Systems, in International Symposium on Low Power Electronics and Design, 2009.
H. N. Patel, Mann, R. W., and Calhoun, B. H., Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
M. Bhargava, Nalam, S., Calhoun, B. H., and Mai, K., An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization, in TECHCON, 2009.
P. Beshay, Bolus, J., Blalock, T., Chandra, V., and Calhoun, B. H., SRAM Sense Amplifier Offset Cancellation Using BTI Stress, in Subthreshold Microelectronics Conference, 2012.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., SRAM-Based NBTI/PBTI Sensor System Design, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
J. Boley and Calhoun, B. H., Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset, in International Symposium on Quality Electronic Design, 2015.
A. Dissanayake, Bowers, S. M., and Calhoun, B. H., Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
B. Calhoun and Chandrakasan, A., Standby Voltage Scaling for Reduced Power, in Custom Integrated Circuits Conference (CICC), 2003, pp. 639-642.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.
S. Khanna, Craig, K., Shakhsheer, Y., Arrabi, S., Lach, J., and Calhoun, B., Stepped Supply Voltage Switching for Energy Constrained Systems, in ISQED, 2011.
S. Li and Calhoun, B. H., Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper), 2020.
B. H. Calhoun, Khanna, S., Mann, R., and Wang, J., Sub-threshold Circuit Design with Shrinking CMOS Devices, in International Symposium on Circuits and Systems, 2009.
B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., Sub-threshold Design: The Challenges of Minimizing Circuit Energy, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.
B. H. Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic, in GOMAC Tech, 2011.
J. F. Ryan and Calhoun, B. H., A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS, in Custom Integrated Circuits Conference (CICC), 2010.
B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors, in International Symposium on Circuits and Systems, 2009.