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R. W. Mann, Wang, J., Nalam, S., Khanna, S., Braceras, G., Pilo, H., and Calhoun, B. H., Impact of circuit assist methods on margin and performance in 6T SRAM, Journal of Solid State Electronics, vol. 54, pp. 1398-1407, 2010.
D. S. Truesdell and Calhoun, B. H., Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
H. Patel, Yahya, F., and Calhoun, B. H., Improving Reliability and Energy Requirements of Memory in Body Sensor Networks., in International Conference on VLSI Design, Kolkata, India, 2016.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress, in CICC, San Jose, CA, 2010.
H. L. Bishop*, Dissanayake*, A., Bowers, S. M., and Calhoun, B. H., An Integrated 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μW at 100ms Latency, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (*Equally-Credited Authors), 2021.
J. Moody, Bassirian, P., Roy, A., Liu, N. X., N Barker, S., Calhoun, B. H., and Bowers, S. M., Interference Robust Detector-First Near-Zero Power Wake-Up Receiver, IEEE Journal of Solid-State Circuits, 2019.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., A Leakage Reduction Methodology for Distributed MTCMOS, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 818-826, 2004.
J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications, in GOMAC Tech, 2014.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B., Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN, in Design Automation and Test Europe, 2013.
H. L. Bishop, Wang, P., Fan, D., Lach, J., and Calhoun, B. H., Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems, in Global Internet of Things Summit (GIoTS), 2018.
, Limits of Bias Based Assist Methods in Nano-Scale 6T SRAM, in ISQED, 2010, pp. 1-8.
B. H. Calhoun, Schurgers, C., Wang, A., and Chandrakasan, A., Low Energy Digital Circuit Design, in AmIware: Hardware Drivers of Ambient Intelligence, and Ouwerkerk, M., Eds. Springer, 2006.
O. Abdelatty, Bishop, H., Shi, Y., Chen, X., Alghaihab, A., Calhoun, B., and Wentzloff, D., A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator, in IEEE European Solid-State Circuits Conference (ESSCIRC), Cracow, Poland, 2019.