VLSI Design Group

Navigation

Search This Site

Publications

Export 169 results:
Author [ Title(Asc)] Type Year
Filters: Author is Benton H. Calhoun  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
6
D. S. Truesdell, Breiholz, J., Kamineni, S., Liu, N. X., Magyar, A., and Calhoun, B. H., A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic (1.63 MB)
X. Liu, Agrawal, A., Tanaka, A., and Calhoun, B. H., A 6nA Fully-Autonomous Triple-Input Hybrid-Inductor-Capacitor Multi-Output Power Management System with Multi-Rail Energy Sharing, All-Rail Cold Startup, and Adaptive Conversion Control for mm-scale Distributed Systems, in 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024.PDF icon A_6nA_Fully Autonomous_Triple-Input_Hybrid-Inductor-Capacitor_Multi-Output_Power_Management_System_with_Multi-Rail_Energy_Sharing_All-Rail_Cold_Startup_and_Adaptive_Conve.pdf (1.55 MB)
S. Gupta, Truesdell, D. S., and Calhoun, B. H., A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.PDF icon A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes.pdf (935.56 KB)
D. S. Truesdell and Calhoun, B. H., A 640 pW 22 pJ/sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25°C Resolution, in IEEE Custom Integrated Circuits Conference (CICC) 2019, Austin, TX, 2019.PDF icon A 640 pW 22 pJ_sample Gate Leakage-Based Digital CMOS Temperature Sensor with 0.25C Resolution.pdf (1.81 MB)
3
D. Duvvuri, Shen, X., Bassirian, P., Bishop, H. L., Liu, X., Chen, C. - H., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.
X. Liu, Truesdell, D. S., Faruqe, O., Parameswaran, L., Rickley, M., Kopanski, A., Cantley, L., Coon, A., Bernasconi, M., Wang, T., and Calhoun, B. H., A 33nW Fully Autonomous SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for mm-scale System-in-Fiber, in IEEE Transactions on Biomedical Circuits and Systems, Invited paper, 2023.PDF icon A_33nW_Fully_Autonomous_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_mm-scale_System-in-Fiber.pdf (16.09 MB)
S. Li, Liu, X., and Calhoun, B. H., A 32nA Fully Autonomous Multi-Input Single-Inductor Multi-Output Energy Harvesting and Power Management Platform with 1.2×10^5 Dynamic Range, Integrated MPPT, and Multi-Modal Cold Start-Up, in IEEE International Solid-State Circuits Conference (ISSCC), 2022.
K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance, Journal of Solid State Circuits, 2014.
2
A. Agrawal, Chen, Z., Desman, B. E., Wang, J., Tanaka, A., Foysal, F., Hess, C. D., Farrell, W., Owens, J., Truesdell, D. S., and Calhoun, B. H., A 2-Dimensional mm-scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6mm x 2.15mm SoC and bySPI chiplets, in 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025.
S. Jocke, Bolus, J., Wooters, S. N., Jurik, A. D., Weaver, A. F., Blalock, T. N., and Calhoun, B. H., A 2.6-μW Sub-threshold Mixed-signal ECG SoC, in Symposium on VLSI Circuits, 2009.
B. H. Calhoun and Chandrakasan, A., A 256kb Sub-threshold SRAM in 65nm CMOS, presented at the 02/2006, IEEE International Solid-State Circuits Conference, 2006, pp. 628-629.
B. H. Calhoun and Chandrakasan, A., A 256kb 65nm Sub-threshold SRAM Design for Ultra-low Voltage Operation, IEEE Journal of Solid-State Circuits (JSSC), vol. 42, pp. 680-688, 2007.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time, IEEE Journal of Solid-State Circuits (JSSC), 2019.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., Chen, X., Wentzloff, D. D., and Calhoun, B. H., A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver, IEEE Journal of Solid-State Circuits, 2021.
P. Wang, Agarwala, R., Ownby, N., Liu, X., and Calhoun, B. H., A 2.3-5.7μW Tri-Modal Self-Adaptive Photoplethysmography Sensor Interface IC for Heart Rate, SpO2 , and Pulse Transit Time Co-Monitoring, IEEE Transactions on Biomedical Circuits and Systems, 2024.

Pages