Robust Low Power VLSI

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P. Beshay, Bolus, J., Blalock, T., Chandra, V., and Calhoun, B. H., “SRAM Sense Amplifier Offset Cancellation Using BTI Stress”, in Subthreshold Microelectronics Conference, 2012.

J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “SRAM-Based NBTI/PBTI Sensor System Design”, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.

A. Dissanayake, Bowers, S. M., and Calhoun, B. H., “Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.

B. H. Calhoun and Chandrakasan, A., “Standby Power Reduction Using Dynamic Voltage Scaling and Flip-Flop Structures”, IEEE Journal of Solid-State Circuits (JSSC), vol. 39, pp. 1504-1511, 2004.

J. Wang and Calhoun, B. H., “Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs”, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.

B. H. Calhoun and Chandrakasan, A., “Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 1673-1679, 2006.

J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array”, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.

S. Li and Calhoun, B. H., “Sub-microAmp Energy Harvesting and Power Management Units for Self-Powered IoT SoCs: Analog vs. Digital Implementations”, in 2020 IEEE Custom Integrated Circuits Conference (CICC), (invited paper), 2020.

X. Liu, Calhoun, B. H., and Li, S., “A Sub-nW 93% Peak Efficiency Buck Converter with Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control”, IEEE Journal of Solid-State Circuits, (invited paper), 2022.

A SubnW 93 Peak Efficiency Buck Converter With Wide Dynamic Range Fast DVFS and Asynchronous Load Transient Control.pdf (3.94 MB)

A. Shrivastava and Calhoun, B. H., “A sub-threshold clock and data recovery circuit for a wireless sensor node”. 2011.

B. H. Calhoun, Wang, A., Verma, N., and Chandrakasan, A., “Sub-threshold Design: The Challenges of Minimizing Circuit Energy”, in International Symposium on Low Power Electronics and Design (ISLPED), 2006, pp. 366-368.

B. H. Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., “A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic”, in GOMAC Tech, 2011.

J. F. Ryan and Calhoun, B. H., “A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS”, in Custom Integrated Circuits Conference (CICC), 2010.

B. H. Calhoun, Bolus, J., Khanna, S., Jurik, A. D., Weaver, A. F., and Blalock, T. N., “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.

P. Beshay, Ryan, J. F., and Calhoun, B. H., “Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry”, in Subthreshold Microelectronics Conference, 2012.

H. N. Patel, Yahya, F. B., and Calhoun, B. H., “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.

B. H. Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., “System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms”, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.

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J. Wang and Calhoun, B. H., “Techniques to Extend Canary-based Standby VDD Scaling for SRAMs to 45nm and Beyond”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2514-2523, 2008.

P. Bassirian, Duvvuri, D., Truesdell, D. S., Liu, N. X., Calhoun, B. H., and Bowers, S. M., “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.

F. B. Yahya, Lukas, C. J., and Calhoun, B. H., “A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things”, Journal of Low Power Electronics & Applications, 2018.

J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., “Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs”, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.

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A. Banerjee and Calhoun, B. H., “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.

A. Wang, Calhoun, B. H., Verma, N., Kwong, J., and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling for Energy Starved Electronics”, in Proc. of GOMAC Tech, 2007.

B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling (UDVS) Using Sub-threshold Operation and Local Voltage Dithering”, IEEE Journal of Solid-State Circuits (JSSC), vol. 41, pp. 238-245, 2006.

B. H. Calhoun and Chandrakasan, A., “Ultra-Dynamic Voltage Scaling Using Sub-threshold Operation and Local Voltage Dithering in 90nm CMOS”, in International Solid State Circuits Conference (ISSCC), 2005, pp. 300-301.

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