VLSI Design Group


Search This Site


Export 159 results:
Author Title Type [ Year(Asc)]
Filters: Author is Benton H. Calhoun  [Clear All Filters]
S. Nalam and Calhoun, B. H., 5T SRAM with Asymmetric Sizing for Improved Read Stability, JSSC, 2011.
B. H. Calhoun, Lach, J., Stankovic, J., Wentzloff, D. D., Whitehouse, K., Barth, A., Brown, J. K., Li, Q., Oh, S., Roberts, N., and Zhang, Y., Body Sensor Networks: A Holistic Approach From Silicon to Users, IEEE Proceedings, 2011.
Y. Zhang and Calhoun, B. H., The Cost of Fixing Hold Time Violations in Sub-threshold Circuits. 2011.
Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., Energy Efficient Design for Body Sensor Nodes, Journal of Low Power Electronics and Applications, 2011.
J. Wang, Hoefler, A., and Calhoun, B. H., An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction, Transactions on VLSI Systems (TVLSI), 2011.
C. T. Murphy, W. Eberhardt, C., Calhoun, B. H., and Mann, D. A., Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception, in Conference on the Biology of Marine Mammals, 2011.
K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation, in Subthreshold Microelectronics Conference, 2011.
A. Shrivastava and Calhoun, B. H., A sub-threshold clock and data recovery circuit for a wireless sensor node. 2011.
B. H. Calhoun, Zhang, Y., Khanna, S., Craig, K., Shakhsheer, Y., and Lach, J., A Sub-Threshold FPGA: Energy-Efficient Reconfigurable Logic, in GOMAC Tech, 2011.
B. H. Calhoun and Brooks, D., Can Subthreshold and Near-Threshold Circuits Go Mainstream?, IEEE Micro, vol. 30, pp. 80-85, 2010.
S. N. Wooters, Calhoun, B. H., and Blalock, T. N., An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores, in TECHCON, 2010.
B. H. Calhoun, Ryan, J., Khanna, S., Putic, M., and Lach, J., Flexible Circuits and Architectures for Ultra Low Power, Proceedings of the IEEE, vol. 98, pp. 267-282, 2010.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., SRAM-Based NBTI/PBTI Sensor System Design, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
J. Wang and Calhoun, B. H., Standby Supply Voltage Minimization for Reliable Nanoscale SRAMs, in Solid State Circuits Technologies, J. W. Swart, Ed. INTECH, 2010.
J. F. Ryan and Calhoun, B. H., A Sub-Threshold FPGA with Low-Swing Dual-VDD Interconnect in 90nm CMOS, in Custom Integrated Circuits Conference (CICC), 2010.
B. H. Calhoun, Khanna, S., Zhang, Y., Ryan, J., and Otis, B., System Design Principles Combining Sub-threshold Circuits and Architectures with Energy Scavening Mechanisms, in International Symposium on Circuits and Systems (ISCAS), Paris, France, 2010, pp. 269-272.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs, Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 1908-1920, 2010.