Robust Low Power VLSI
VLSI Design Group

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Publications

2012
P. Beshay, Bolus, J., Blalock, T., Chandra, V., and Calhoun, B. H., “SRAM Sense Amplifier Offset Cancellation Using BTI Stress”, in Subthreshold Microelectronics Conference, 2012.
P. Beshay, Ryan, J. F., and Calhoun, B. H., “Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry”, in Subthreshold Microelectronics Conference, 2012.
S. N. Wooters, Cabe, A. C., Qi, Z., Wang, J., Mann, R. W., Calhoun, B. H., Stan, M. R., and Blalock, T. N., “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.
2013
N. Gilbert, Zhang, Y., Dinh, J., Calhoun, B., and Hollmer, S., “A 0.6V 8 pJ/write Non-Volatile CBRAM Macro Embedded in a Body Sensor Node for Ultra Low Energy Applications”, in Symposium on VLSI Circuits, 2013.
A. Shrivastava, Pandey, J., Otis, B., and Calhoun, B. H., “A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node”, in VLSI Design Conference, 2013.
Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
A. Shrivastava and Calhoun, B. H., “A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications”, 2013.
P. Beshay, Ryan, J. F., and Calhoun, B. H., “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
Y. Zhang and Calhoun, B. H., “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B., “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.
A. Banerjee and Calhoun, B. H., “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
J. Boley, Beshay, P., and Calhoun, B., “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
2014
A. Shrivastava, Wentzloff, D., and Calhoun, B. H., “A 10mV-Input Boost Converter with Inductor Peak Current Control and Zero Detection for Thermoelectric Energy Harvesting”, in IEEE Custom Integrated Circuits Conference (CICC), 2014.
A. Shrivastava, Ramadass, Y. K., Khanna, S., Bartling, S., and Calhoun, B. H., “A 1.2μW SIMO Energy Harvesting and Power Management Unit with Constant Peak Inductor Current Control Achieving 83-92% Efficiency Across Wide Input and Output Voltages”, in Symposium on VLSI Circuits, 2014.
K. Craig, Shakhsheer, Y., Arrabi, S., Khanna, S., Lach, J., and Calhoun, B. H., “A 32b 90nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation from Sub-threshold to High Performance”, Journal of Solid State Circuits, 2014.
J. .Bolus, Calhoun, B. H., and .Blalock, T., “39 fJ/bit On-Chip Identification of Wireless Sensors Based on Manufacturing Variation”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 16, 2014.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
Y. Zhang and Calhoun, B. H., “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits”, in International Symposium on Quality Electronic Design (ISQED), 2014.
S. Arrabi, Moore, D., Wang, L., Skadron, K., and Calhoun, B. H., “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems”, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
J. J. Granacki, Calhoun, B. H., Dasu, A. R., Jagasivamani, M., McIlrath, L., and Fritze, M., “LEDRA: A 3DIC Ultra-Low Power FPGA Architecture for DoD Applications”, in GOMAC Tech, 2014.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
S. Khanna, Nalam, S. V., and Calhoun, B. H., “Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories”, in VLSI Design Conference, 2014.
A. Klinefelter and Calhoun, B. H., “A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs”, in S3S Conference, Monterey, CA, 2014.
A. Banerjee, Sinangil, M., Poulton, J., Gray, C. T., and Calhoun, B. H., “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs”, in International Symposium on Quality Electronic Design (ISQED), 2014.

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