VLSI Design Group

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Conference Paper
K. Flynn, Ownby, N., Wang, P., and Calhoun, B. H., Modeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypes, in IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., Modeling SRAM Dynamic VMIN, in International Conference on IC Design and Technology (ICICDT), 2014.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., MSN: Memory Sensor for NBTI, in Techcon, 2009.
A. Dissanayake, Bishop, H. L., Moody, J., Muhlbauer, H., Calhoun, B. H., and Bowers, S. M., A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
D. S. Truesdell, Liu, X., Breiholz, J., Gupta, S., Li, S., and Calhoun, B. H., NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.PDF icon NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
R. Mann and Calhoun, B., New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm, in ISQED, 2011.
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., An Open-source Framework for Autonomous SoC Design with Analog Block Generation, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
K. Craig, Shakhsheer, Y., and Calhoun, B. H., Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation, in International Symposium on Low Power Electronics and Design, 2012.
K. Craig, Shakhsheer, Y., Khanna, S., and Calhoun, B. H., Optimal Power Switch Design for Panoptic Dynamic Voltage Scaling Enabling Subthreshold Operation, in Subthreshold Microelectronics Conference, 2011.
H. Qi, Ayorinde, O., Huang, Y., and Calhoun, B., Optimizing energy efficient low-swing interconnect for sub-threshold FPGAs, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, UK, 2015.
H. Patel, Yahya, F., and Calhoun, B., Optimizing SRAM Bitcell Reliability and Energy for IoT Applications, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
M. Putic, Di, L., Calhoun, B. H., and Lach, andJohn, Panoptic DVS: A Fine-Grained Dynamic Voltage Scaling Framework for Energy Scalable CMOS Design, in International Conference on Computer Design (ICCD), 2009, pp. 491-497.
S. Li, Roy, A., and Calhoun, B. H., A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
S. Khanna, Nalam, S. V., and Calhoun, B. H., Pipelined Non-Strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories, in VLSI Design Conference, 2014.
D. Akella Kamakshi, Guo, X., Patel, H. N., Stan, M. R., and Calhoun, B. H., A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
L. Di, Putic, M., Lach, J., and Calhoun, B. H., Power Switch Characterization for Fine-Grained Dynamic Voltage Scaling, in International Conference on Computer Design, pages 605-611, 2008.
K. Craig, Shakhsheer, Y., Khanna, S., Arrabi, S., Lach, J., Calhoun, B. H., and Kosonocky, S., A Programmable Resistive Power Grid for Post-Fabrication Flexibility and Energy Tradeoffs, in International Symposium on Low Power Electronics and Design, 2012.
A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design, in International Conference on VLSI Design, India, 2008, pp. 131-136.
A. Klinefelter and Calhoun, B. H., A Reduced-Memory FIR Filter Using Approximate Coefficients for Ultra-Low Power SoCs, in S3S Conference, Monterey, CA, 2014.
B. H. Meyer, Skadron, K., George, N., Calhoun, B. H., and Lach, J., Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication, in Design Automation and Test in Europe (DATE), 2011.
L. Szafaryn, Chen, J., Calhoun, B. H., Lach, J., Skadron, K., and Meyer, B. H., Reducing the Cost of Safety-Critical Systems with On-Demand Redundancy, in SRC Techcon, 2012.
B. H. Calhoun, Arrabi, S., Khanna, S., Shakhsheer, Y., Craig, K., Ryan, J., and Lach, J., REESES: Rapid Efficient Energy Scalable ElectronicS, in GOMAC Tech, 2010.
A. Banerjee, Sinangil, M., Poulton, J., Gray, C. T., and Calhoun, B. H., A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs, in International Symposium on Quality Electronic Design (ISQED), 2014.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM, in Design Automation Conference (DAC), 2014.

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