Publications
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, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications”, in 32nd International Conference on VLSI Design, 2019.
, “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM”, in Design Automation and Test Europe (DATE), 2011.
, “Dynamic Write Limited Minimum Operating Voltage for Nanoscale SRAM”, in Design Automation and Test Europe (DATE), 2011.
, “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
, “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
, “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
, “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
, “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
, “Error-Energy Analysis of Hardware Logarithmic Approximation Methods for Low Power Applications”, in International Symposium on Circuits and Systems (ISCAS), 2015.
, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores”, in TECHCON, 2010.
, “Exploring Circuit Robustness to Power Supply Variation in Low-Voltage Latch and Register-Based Digital Systems”, in IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
, “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
, “Fast, Accurate Variation-Aware Path Timing Computation for Sub-threshold Circuits”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “Fast Algorithm for Clock Grid Simulation”, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
, “Fast Algorithm for Clock Grid Simulation”, in European Solid State Circuits Conference (ESSCIRC), 2002, pp. 771-774.
, “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems”, in International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014.
, “Flow-induced Vibrations of Pinniped Vibrissae: Effects of Angular Orientation and Implications for Hydrodynamic Reception”, in Conference on the Biology of Marine Mammals, 2011.
, “Graph Coloring using Coupled Oscillator-based Dynamical Systems”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
, “Hold Time Closure for Subthreshold Circuits Using a Two-Phase, Latch Based Timing Method”, in S3S Conference, Monterey, California, 2013.
, “Improving Dynamic Leakage Suppression Logic with Forward Body Bias in 65nm CMOS”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2019.
, “Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.”, in International Conference on VLSI Design, Kolkata, India, 2016.
, “Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress”, in CICC, San Jose, CA, 2010.
, “An Integrated 2.4GHz -91.5dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver Achieving 2μW at 100ms Latency”, in IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA (*Equally-Credited Authors), 2021.