Robust Low Power VLSI
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K. Craig, Shakhsheer, Y., and Calhoun, B. H., “Optimal Power Switch Design for Dynamic Voltage Scaling from High Performance to Subthreshold Operation”, in International Symposium on Low Power Electronics and Design, 2012.
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
T. Ajayi, Kamineni, S., Cherivirala, Y. K., Fayazi, M., Kwon, K., Saligane, M., Gupta, S., Chen, C. - H., Sylvester, D., Blaauw, D., Dreslinski, Jr, R., Calhoun, B., and Wentzloff, D. D., “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
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R. W. Mann, Hook, T. B., Nguyen, P., and Calhoun, B. H., “Non-Random Device Mismatch Considerations in Nanoscale SRAM”, IEEE Transactions of VLSI Systems (TVLSI), 2011.
R. Mann and Calhoun, B., “New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm”, in ISQED, 2011.
P. Bassirian, Moody, J., Lu, R., Gao, A., Manzaneque, T., Roy, A., N Barker, S., Calhoun, B. H., Gong, S., and Bowers, S. M., “Nanowatt-Level Wakeup Receiver Front Ends Using MEMS Resonators for Impedance Transformation”, IEEE Transactions on Microwave Theory and Techniques, 2019.
D. S. Truesdell, Liu, X., Breiholz, J., Gupta, S., Li, S., and Calhoun, B. H., “NanoWattch: A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling”, in 2022 IEEE Symposium on VLSI Circuits (VLSI), (Equally-Credited Authors), 2022.PDF icon NanoWattch A Self-Powered 3-nW RISC-V SoC Operable from 160mV Photovoltaic Input with Integrated Temperature Sensing and Adaptive Performance Scaling.pdf (11.11 MB)
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A. Banerjee, Kamineni, S., and Calhoun, B. H., “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
A. Dissanayake, Bishop, H. L., Moody, J., Muhlbauer, H., Calhoun, B. H., and Bowers, S. M., “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., “MSN: Memory Sensor for NBTI”, in Techcon, 2009.
S. Z. Ahmed, Tan, Y., Truesdell, D. S., Calhoun, B. H., and Ghosh, A., “Modeling tunnel field effect transistors-from interface chemistry to non-idealities to circuit level performance”, Journal of Applied Physics, 2018.
C. J. Lukas, Yahya, F. B., and Calhoun, B. H., “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems”, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
J. Boley, Chandra, V., Aitken, R., and Calhoun, B. H., “Modeling SRAM Dynamic VMIN”, in International Conference on IC Design and Technology (ICICDT), 2014.
K. Flynn, Ownby, N., Wang, P., and Calhoun, B. H., “Modeling Energy-Aware Photoplethysmography Hardware for Personalized Health Care Applications Across Skin Phototypes”, in IEEE Biomedical Circuits and Systems Conference (BioCAS), 2021.
N. Ownby, Flynn, K., and Calhoun, B. H., “Modeling Energy Aware Photoplethsmography for Personalized Healthcare Applications”, in IEEE Transactions on Biomedical Circuits and Systems, 2022.
A. Shrivastava and Calhoun, B. H., “Modeling DC-DC Converter Efficiency and Power Management in Ultra Low Power Systems”, in Subthreshold Microelectronics Conference, 2012.
B. H. Calhoun, Wang, A., and Chandrakasan, A., “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.
B. H. Calhoun, Wang, A., and Chandrakasan, A., “Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits”, IEEE Journal of Solid-State Circuits (JSSC), vol. 40, pp. 1778-1786, 2005.
D. Kamakshi, Fojtik, M., Khailany, B., Kudva, S., Zhou, Y., and Calhoun, B. H., “Modeling and Analysis of Power Supply Noise Tolerance with Fine-grained GALS Adaptive Clocks”, in ASYNC, 2016.
A. D. Jurik, Bolus, J., Weaver, A. F., Calhoun, B. H., and Blalock., T. N., “Mobile Health Monitoring Through Biotelemetry”, in Bodynets, 2009.
D. S. Truesdell, Ahmed, S. Z., Ghosh, A. W., and Calhoun, B. H., “Minimum-Energy Digital Computing with Steep Subthreshold Swing Tunnel FETs”, IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), 2020.PDF icon Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs.pdf (1.02 MB)
J. Wang and Calhoun, B. H., “Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations”, Transactions on VLSI Systems (TVLSI), 2011.
J. F. Ryan and Calhoun, B. H., “Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation”, in International Symposium on Quality Electronic Design, 2008, pp. 127-132.

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