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“Asymmetric 6T SRAM with Two-phase Write and Split Bitline Differential Sensing for Low Voltage Operation”, in ISQED, 2010, pp. 139-146.
, “Asymmetric Sizing in a 45nm 5T SRAM to Improve Read Stability over 6T”, in CICC, 2009, pp. 709-712.
, “AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells”, in Design, Automation and Test in Europe Conference (DATE), 2023, 2023.
AuxcellGen-A Framework for Autonomous Generation of Analog and Memory Unit Cells.pdf (3.37 MB)
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“A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
, “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.
, “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.
, “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.
, “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
, “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
, “A Bio-Inspired Artificial Whisker for Fluid Motion Sensing with Increased Sensitivity and Reliability”, in IEEE Sensors, Limrick, Ireland, 2011.
, “Body Area Sensor Networks: Challenges and Opportunities”, Computer, vol. 42, pp. 58–65, 2009.
, “Body Sensor Networks: A Holistic Approach From Silicon to Users”, IEEE Proceedings, 2011.
, “Can Subthreshold and Near-Threshold Circuits Go Mainstream?”, IEEE Micro, vol. 30, pp. 80-85, 2010.
, “Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM”, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
, “A Capacitance-Based Whisker-like Artificial Sensor for Fluid Motion Sensing”, in IEEE Sensors, 2010.
, “Channel Length Sizing for Power Minimization in Leakage-Dominated Digital Circuits”, in IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018.
, “Characterization of Stacked PV Cell Configurations in a Deep N-Well 65nm CMOS Technology”, in 2025 IEEE International Symposium on Circuits and Systems (ISCAS), In Press.
, “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits”, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.
, “Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits”, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.
, “A Charge Pump Based Receiver Circuit for a Voltage Scaled Interconnect”, in International Symposium on Low Power Electronics and Design, 2012.
, “Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation”, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.
, “Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation”, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.
, “A comprehensive analysis of Auger generation impacted planar Tunnel FETs”, Solid-State Electronics, 2020.
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