Publications
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Author [ Title] Type Year Filters: First Letter Of Last Name is B [Clear All Filters]
“Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
, “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
, “Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry”, in Subthreshold Microelectronics Conference, 2012.
, “A Sub-µW Energy-Performance-Aware IoT SoC with a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization”, IEEE Journal of Solid-State Circuits, 2024. A_Sub-_mu_W_Energy-Performance-Aware_IoT_SoC_With_a_Triple_Mode_Power_Management_Unit_for_System_Performance_Scaling_Fast_DVFS_and_Energy_Minimization.pdf (7.38 MB)
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), vol. 20, p. 12, 2012.
, “Tracking On-Chip Age Using Distributed, Embedded Sensors”, Transactions on VLSI Systems (TVLSI), 2011.
, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
, “An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 4, p. 19, 2014.
, “Using synchronized oscillators to compute the maximum independent set”, Nature Communications, 2020.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization”, Transactions of Very Large Scale Integration Systems, 2015.
, “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization”, Transactions of Very Large Scale Integration Systems, 2015.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
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