Publications
] , “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
, “A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs”, in 19th International Symposium on Quality Electronic Design (ISQED), 2018.
, “A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things”, Journal of Low Power Electronics & Applications, 2018.
, “An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches”, in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.
, “A 256kb 6T self-tuning SRAM with extended 0.38V–1.2V operating range using multiple read/write assists and VMIN tracking canary sensors”, in 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, 2017.
, “A 4.4 nW Lossless Sensor Data Compression Accelerator for 2.9x System Power Reduction in Wireless Body Sensors”, in 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 2017.
, “A 71% Efficient Energy Harvesting and Power Management Unit for Sub-µW Power Biomedical Applications”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
, “An 8.3 nW -72 dBm Event Driven IoE Wake Up Receiver RF Front End”, in 2017 European Microwave Integrated Circuit Conference (EuMIC), Nuremberg, Germany, 2017.
, “Auger Effect Limited Performance in Tunnel Field Effect Transistors”, in 5th Berkeley Symposium on Energy Efficient Electronics & Steep Transistors Workshop, Berkeley, CA, 2017.
, “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.
, “FAR: A 4.12uW Ferro-electric Auto-Recovery for Battery-less BSN SoCs”, in 2017 IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
, “Modeling Trans-threshold Correlations for Reducing Functional Test Time in Ultra-Low Power Systems”, in 2017 IEEE International Test Conference (ITC), Fort Worth, TX, USA, 2017.
, “Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications”, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.
, “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.
, “An Ultra-Low-Power FPGA for IoT Applications”, in S3S 2017, 2017.
, “A 0.2 V, 23 nW CMOS Temperature Sensor for Ultra-Low-Power IoT Applications”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “A 1.3μW, 5pJ/cycle sub-threshold MSP430 processor in 90nm xLP FDSOI for energy-efficient IoT applications”, in International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2016.
, “A 1.5nW, 32.768kHz XTAL Oscillator Operational from 0.3V Supply”, IEEE Journal of Solid-State Circuits (JSSC), vol. 51, 2016.
, “A 236nW -56.5dBm Sensitivity Self-Powered Bluetooth Low-Energy Wakeup Receiver in 65nm CMOS”, in IEEE International Solid-State Circuits Conference (ISSCC), 2016.
, “A 36nW, 7 ppm/oC Fully On-Chip Clock Source System for Ultra-Low Power Applications”, Journal of Low Power Electronics and Applications (JLPEA), vol. 6, 2016.
, “A 55nm Ultra Low Leakage Deeply Depleted Channel Technology Optimized for Energy Minimization in Subthreshold SRAM and Logic”, in European Solid State Circuits Conference (ESSCIRC), 2016.
, “A Design and Theoretical Analysis of a 145 mV to 1.2 V Single-Ended Level Converter Circuit for Ultra-Low Power Low Voltage ICs”, J. Low Power Electron. Appl. (JLPEA), vol. 6, 2016.
, “Design Optimization of Register File Throughput and Energy using a Virtual Prototyping (ViPro) Tool”, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
, “Development of an artificial sensor for hydrodynamic detection inspired by a seal’s whisker array”, Bioinspiration and Biomimetics, 2016.
, “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.