Robust Low Power VLSI

VLSI Design Group

Search This Site

Publications

Export 8 results:

Filters: Author is James Boley [Clear All Filters]

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

6

A. Klinefelter, Roberts, N., Shakhsheer, Y., Gonzalez, P., Shrivastava, A., Roy, A., Craig, K., Faisal, M., Boley, J., Oh, S., Zhang, Y., Akella, D., Wentzloff, D. D., and Calhoun, B., “A 6.45 μW Self-Powered IoT SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios”, in ISSCC, San Francisco, CA, 2015.

A. Roy, Klinefelter, A., Yahya, F., Chen, X., Gonzalez, P., Lukas, C. J., Akella, D., Boley, J., Craig, K., Faisal, M., Oh, S., Roberts, N., Shakhsheer, Y., Shrivastava, A., Vasudevan, D., Wentzloff, D. D., and Calhoun, B., “A 6.45μW Self-Powered SoC with Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems”, IEEE Transactions on Biomedical Circuits and Systems, vol. 9, pp. 862-874, 2015.

A

J. Boley, Wang, J., and Calhoun, B. H., “Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM Vmin”, Journal of Low Power Electronics and Applications, 2012.

B

Y. Zhang, Zhang, F., Shakhsheer, Y., Silver, J. D., Klinefelter, A., Nagaraju, M., Boley, J., Pandey, J., Shrivastava, A., Carlson, E. J., Wood, A., Calhoun, B. H., and Otis, B. P., “A Batteryless 19 uW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications”, Journal of Solid State Circuits, vol. 48, pp. 199-213, 2013.

F. Zhang, Zhang, Y., Silver, J., Shakhsheer, Y., Nagaraju, M., Klinefelter, A., Pandey, J., Boley, J., Carlson, E., Shrivastava, A., Otis, B., and Calhoun, B., “A Batteryless 19uW MICS/ISM-Band Energy Harvesting Body Area Sensor Node SoC”, in ISSCC, San Francisco, 2012.

L

J. Boley, Chandra, V., Aitken, R., and Calhoun, B., “Leveraging Sensitivity Analysis for Fast, Accurate Estimation of SRAM Dynamic VMIN”, in Design Automation and Test Europe, 2013.

V

J. Boley, Beshay, P., and Calhoun, B. H., “Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization”, Transactions of Very Large Scale Integration Systems, 2015.

J. Boley, Beshay, P., and Calhoun, B., “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.