VLSI Design Group

Navigation

Search This Site

Publications

Export 147 results:
Author [ Title(Asc)] Type Year
Filters: Author is Benton H. Calhoun  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
D
S. Gupta and Calhoun, B. H., Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
S. Gupta and Calhoun, B. H., Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
A. Banerjee, A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications, in 32nd International Conference on VLSI Design, 2019.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM, in ISLPED, 2014.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
P. Beshay, Ryan, J. F., and Calhoun, B. H., A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers, Journal of Low Power Electronics and Applications, 2013.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Device Sizing for Minimum Energy Operation in Subthreshold Circuits, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes, in International Conference on VLSI Design, 2004, pp. 361-367.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
A. Shrivastava and Calhoun, B. H., A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications, 2013.
L. Wang, Skadron, K., and Calhoun, B. H., Dark vs. Dim Silicon and Near-Threshold Computing, in Dark Silicon Workshop (DaSi), 2012.
C
X. Chen, Alghaihab, A., Shi, Y., Truesdell, D. S., Calhoun, B. H., and Wentzloff, D. D., A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets, IEEE Journal of Solid-State Circuits, 2021.
A. Alghaihab, Chen, X., Shi, Y., Truesdell, D. S., Calhoun, B. H., and Wentzloff, D. D., A Crystal-Less BLE Transmitter with -86dBm Frequency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
Y. Zhang and Calhoun, B. H., The Cost of Fixing Hold Time Violations in Sub-threshold Circuits. 2011.
S. Z. Ahmed, Truesdell, D. S., Tan, Y., Calhoun, B. H., and Ghosh, A. W., A comprehensive analysis of Auger generation impacted planar Tunnel FETs, Solid-State Electronics, 2020.
F. B. Yahya, Patel, H. N., Chandra, V., and Calhoun, B. H., Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.
B. H. Calhoun and Chandrakasan, A., Characterizing and Modeling Minimum Energy Operation for Subthreshold Circuits, in International Symposium on Low Power Electronics and Design, 2004, pp. 90-95.

Pages