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Author Title [ Type(Desc)] Year
Filters: Author is Jiajing Wang  [Clear All Filters]
Conference Paper
J. F. Ryan, Wang, J., and Calhoun, B. H., Analyzing and Modeling Process Balance for Sub-threshold Circuit Design, in GLSVLSI, 2007, pp. 275-280.
J. Wang and Calhoun, B. H., Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM, in Custom Integrated Circuits Conference (CICC), 2007, pp. 29-32.
J. Wang and Calhoun, B. H., An Enhanced Adaptive Canary System for SRAM Standby Power Reduction, in TECHCON, 2008.
J. Wang, Nalam, S., Qi, J., Mann, R. W., Stan, M., and Calhoun, B. H., Improving SRAM Vmin and Yield by Using Variation-Aware BTI Stress, in CICC, San Jose, CA, 2010.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., MSN: Memory Sensor for NBTI, in Techcon, 2009.
A. Singhee, Wang, J., Calhoun, B. H., and Rutenbar, R. A., Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design, in International Conference on VLSI Design, India, 2008, pp. 131-136.
J. Qi, Wang, J., Calhoun, B. H., and Stan, M., SRAM-Based NBTI/PBTI Sensor System Design, in Design Automation Conference (DAC), San Diego, CA, 2010, pp. 849-852.
J. Wang, Singhee, A., Rutenbar, R. A., and Calhoun, B. H., Statistical Modeling for the Minimum Standby Supply Voltage of a Full SRAM Array, in European Solid State Circuits Conference (ESSCIRC), 2007, pp. 400-403.