Robust Low Power VLSI

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F. Yahya, Lukas, C. J., Breiholz, J., Roy, A., Patel, H. N., Liu, N. X., Chen, X., Kosari, A., Li, S., Akella, D., Ayorinde, O., Wentzloff, D. D., and Calhoun, B. H., “A battery-less 507nW SoC with integrated platform power manager and SiP interfaces”, in 2017 Symposium on VLSI Circuits, Kyoto, Japan, 2017.

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F. B. Yahya, Patel, H. N., Chandra, V., and Calhoun, B. H., “Combining SRAM Read/Write Assist Techniques for Near/Sub-Threshold Voltage Operation”, in 6th Asia Symposium on Quality Electronic Design (ASQED 2015), Kuala Lumpur, Malaysia, 2015.

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H. N. Patel, Mann, R. W., and Calhoun, B. H., “Soft Errors: Reliability Challenges in Energy-Constrained ULP Body Sensor Networks Applications”, in 23rd IEEE International Symposium on On-Line Testing and Robust System Design, Thessaloniki, Greece, 2017.

H. N. Patel, Yahya, F. B., and Calhoun, B. H., “Subthreshold SRAM: Challenges, Design Decisions, and Solutions”, in 60th IEEE International Midwest Symposium on Circuits and Systems, Boston, MA, USA, 2017.