Publications
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, “An Open-source Framework for Autonomous SoC Design with Analog Block Generation”, in 28th IFIP/IEEE International Conference on Very Large Scale Integration, Salt Lake City, UT, USA. (Nominated for Best Paper Award), 2020.
, “A Reverse Write Assist Circuit for SRAM Dynamic Write VMIN Tracking using Canary SRAMs”, in International Symposium on Quality Electronic Design (ISQED), 2014.
, “Self Calibrated Dynamic Write Margin Sensor for Low Power Read/Write Operations in Sub-32nm SRAM”, in Design Automation Conference (DAC), 2014.
, “A Self-Powered SoC with Distributed Cooperative Energy Harvesting and Multi-Chip Power Management for System-in-Fiber”, in IEEE International Solid-State Circuits Conference (ISSCC), 2023.
15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB)
15.1_A_Self-Powered_SoC_with_Distributed_Cooperative_Energy_Harvesting_and_Multi-Chip_Power_Management_for_System-in-Fiber.pdf (1.51 MB), “An SRAM Prototyping Tool for Rapid Sub-32nm Design Exploration and Optimization”, in TECHCON, 2009.
, “SRAM Sense Amplifier Offset Cancellation Using BTI Stress”, in Subthreshold Microelectronics Conference, 2012.
, “SRAM Sense Amplifier Offset Cancellation Using BTI Stress”, in Subthreshold Microelectronics Conference, 2012.
, “SRAM Sense Amplifier Offset Cancellation Using BTI Stress”, in Subthreshold Microelectronics Conference, 2012.
, “Stack Based Sense Amplifier Designs for Reducing Input-Referred Offset”, in International Symposium on Quality Electronic Design, 2015.
, “Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
, “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
, “Sub-threshold Operation and Cross-Hierarchy Design for Ultra Low Power Wearable Sensors”, in International Symposium on Circuits and Systems, 2009.
, “Sub-threshold Sense Amplifier Compensation Using Auto-zeroing Circuitry”, in Subthreshold Microelectronics Conference, 2012.
, “A Technology-Agnostic Simulation Environment (TASE) for Iterative Custom IC Design across Processes”, in ICCD, 2009, pp. 523-528.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A Temperature-robust 27.6nW -65dBm Wakeup Receiver at 9.6GHz X Band”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “An Ultra Low Energy 9T Half-select-free Subthreshold SRAM bitcell”, in S3S, Monterey, CA, 2013.
, “Virtual Prototyper (ViPro): An Early Design Space Exploration and Optimization Tool for SRAM Designers”, in Design Automation Conference (DAC), 2010, pp. 138-143.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “Virtual Prototyping (ViPro) Tool for Memory Subsystem Design Exploration and Optimization”, in SRC TECHCON, 2013.
, “Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform”, IEEE Hot Chips 32 Symposium (HCS). 2020.
, “Multiple Combined Write-Read Peripheral Assists in 6T FinFET SRAMs for Low-VMIN IoT and Cognitive Applications”, Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED). IEEE, 2018.
, “A 0.5 V 68 nW ECG Monitoring Analog Front-End for Arrhythmia Diagnosis”, Journal of Low Power Electronics and Applications (JLPEA), 2018.
, “A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, IEEE Journal of Solid-State Circuits, 2021.
, “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.