Publications
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, “A Crystal-Less BLE Transmitter with -86dBm Frequency-Hopping Back-Channel WRX and Over-the-Air Clock Recovery from a GFSK-Modulated BLE Packet”, in 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020.
, “A Crystal-Less BLE Transmitter with Clock Recovery from GFSK-Modulated BLE Packets”, IEEE Journal of Solid-State Circuits, 2021.
, “Dark vs. Dim Silicon and Near-Threshold Computing”, in Dark Silicon Workshop (DaSi), 2012.
, “A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications”, 2013.
, “Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks”, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
, “Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes”, in International Conference on VLSI Design, 2004, pp. 361-367.
, “Design Considerations for Ultra-low Energy Wireless Microsensor Nodes”, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
, “Design Methodology for Fine-Grained Leakage Control in MTCMOS”, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
, “Device Sizing for Minimum Energy Operation in Subthreshold Circuits”, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
, “A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers”, Journal of Low Power Electronics and Applications, 2013.
, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS”, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
, “A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM”, in ISLPED, 2014.
, “A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications”, in 32nd International Conference on VLSI Design, 2019.
, “Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB), “Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs”, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021. Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB), “Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae”, PLOS One, vol. Vol. 8, No. 7, 2013.
, “Energy Efficient Design for Body Sensor Nodes”, Journal of Low Power Electronics and Applications, 2011.
, “Energy-Efficient Link Layer for Wireless Microsensor Networks”, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
, “An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating”, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
, “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
, “An Enhanced Adaptive Canary System for SRAM Standby Power Reduction”, in TECHCON, 2008.
, “An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction”, Transactions on VLSI Systems (TVLSI), 2011.