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D
L. Wang, Skadron, K., and Calhoun, B. H., Dark vs. Dim Silicon and Near-Threshold Computing, in Dark Silicon Workshop (DaSi), 2012.
A. Shrivastava and Calhoun, B. H., A DC-DC Converter Efficiency Model for System Level Analysis in Ultra Low Power Applications, 2013.
E. Shih, Cho, S. - H., Lee, F. S., Calhoun, B. H., and Chandrakasan, A., Design Considerations for Energy-Efficient Radios in Wireless Microsensor Networks, Journal of VLSI Signal Processing, vol. 37, pp. 77-94, 2004.
D. D. Wentzloff, Calhoun, B. H., Min, R., Wang, A., Ickes, N., and Chandrakasan, A. P., Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes, in International Conference on VLSI Design, 2004, pp. 361-367.
B. H. Calhoun, Daly, D. D., Verma, N., Finchelstein, D., Wentzloff, D. D., Wang, A., Cho, S. - H., and Chandrakasan, A., Design Considerations for Ultra-low Energy Wireless Microsensor Nodes, IEEE Transactions on Computers, vol. 54, pp. 727-740, 2005.
B. H. Calhoun, Honore, F. A., and Chandrakasan, A., Design Methodology for Fine-Grained Leakage Control in MTCMOS, in International Symposium on Low Power Electronics and Design (ISLPED), 2003, pp. 104-109.
B. H. Calhoun, Design Principles for Digital CMOS Integrated Circuit Design. NTS Press, 2012.
B. H. Calhoun, Wang, A., and Chandrakasan, A., Device Sizing for Minimum Energy Operation in Subthreshold Circuits, in Custom Integrated Circuits Conference (CICC), 2004, pp. 95-98.
P. Beshay, Ryan, J. F., and Calhoun, B. H., A Digital Auto-Zeroing Circuit to Reduce Offset in Sub-threshold Sense Amplifiers, Journal of Low Power Electronics and Applications, 2013.
B. H. Calhoun, Cao, X. Li Yu, Mai, K., Pileggi, L. T., Rutenbar, R. A., and Shepard, K. L., Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS, Proceedings of the IEEE (Special Issue on Integrated Electronics: Beyond Moore’s Law), vol. 96, pp. 343-365, 2008.
P. Beshay, Chandra, V., Aitken, R., and Calhoun, B. H., A Digital Dynamic Write Margin Sensor for Low Power Read/Write Operations in 28nm SRAM, in ISLPED, 2014.
A. Banerjee, A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning Applications, in 32nd International Conference on VLSI Design, 2019.
S. Gupta and Calhoun, B. H., Dynamic Read VMIN and Yield Estimation for Nanoscale SRAMs, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Read VMIN and Yield Estimation of Nanoscale SRAMs.pdf (3.72 MB)
S. Gupta and Calhoun, B. H., Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs, IEEE Transactions on Circuits and Systems I: Regular Papers, 2021.PDF icon Dynamic Write VMIN and Yield Estimation for Nanoscale SRAMs.pdf (4.55 MB)
E
C. T. Murphy, Eberhardt, W. C., Calhoun, B. H., Mann, K. A., and Mann, D. A., Effect of Angle on Flow-Induced Vibrations of Pinniped Vibrissae, PLOS One, vol. Vol. 8, No. 7, 2013.
Y. Zhang, Shakhsheer, Y., Barth, A. T., Powell, Jr., H. C., Ridenour, S. A., Hanson, M. A., Lach, J., and Calhoun, B. H., Energy Efficient Design for Body Sensor Nodes, Journal of Low Power Electronics and Applications, 2011.
E. Shih, Calhoun, B. H., Cho, S. - H., and Chandrakasan, A., Energy-Efficient Link Layer for Wireless Microsensor Networks, in IEEE Computer Society Workshop on VLSI, 2001, pp. 16-21.
H. Qi, Ayorinde, O., and Calhoun, B. H., An Energy-Efficient Near/Sub-Threshold FPGA Interconnect Architecture Using Dynamic Voltage Scaling and Power-Gating, in International Conference on Field-Programmable Technology (ICFPT 2016), Xi’an, China, 2016.
S. N. Wooters, Calhoun, B. H., and Blalock, T. N., An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 290-294, 2010.
J. Wang and Calhoun, B. H., An Enhanced Adaptive Canary System for SRAM Standby Power Reduction, in TECHCON, 2008.
J. Wang, Hoefler, A., and Calhoun, B. H., An Enhanced Canary-based System with BIST for SRAM Standby Power Reduction, Transactions on VLSI Systems (TVLSI), 2011.
M. Guevara, Marino, M. D., Meng, J., Satyamoorthy, P., Szafaryn, L. G., Wu, P., Meyer, B., Skadron, K., Lach, J., and Calhoun, B. H., Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores, in TECHCON, 2010.

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