Robust Low Power VLSI
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A. Dissanayake, Bowers, S. M., and Calhoun, B. H., “Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design”, in 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
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A. Dissanayake, Bishop, H. L., Moody, J., Muhlbauer, H., Calhoun, B. H., and Bowers, S. M., “A Multichannel, MEMS-less -99dBm 260nW Bit-level Duty Cycled Wakeup Receiver”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
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J. Moody, Dissanayake, A., Bishop, H. L., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A Highly Re-configurable Bit-level Duty Cycled TRF Receiver Achieving -106 dBm Sensitivity and 33 nW Average Power Consumption”, IEEE Solid-State Circuits Letters (SSCL), Special Issue on VLSI (invited paper), 2019.
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P. Wang, Agarwala, R., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., “A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, in 2020 IEEE Symposium on VLSI Circuits (VLSI), 2020.
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D. Duvvuri, Shen, X., Bassirian, P., Bishop, H. L., Liu, X., Chen, C. - H., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A 366 nW, -74.5 dBm Sensitivity Antenna-Coupled Wakeup Receiver at 4.9 GHz with Integrated Voltage Regulation and References”, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, 2021.
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N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., Chen, X., Wentzloff, D. D., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and 8 µs Start-Up Time”, in IEEE European Solid-State Circuits Conference (ESSCIRC), Dresden, Germany, 2018.
N. X. Liu, Agarwala, R., Dissanayake, A., Truesdell, D. S., Kamineni, S., and Calhoun, B. H., “A 2.5 ppm/°C 1.05 MHz Relaxation Oscillator with Dynamic Frequency-Error Compensation and Fast Start-Up Time”, IEEE Journal of Solid-State Circuits (JSSC), 2019.
A. Dissanayake, Bishop, H. L., Bowers, S. M., and Calhoun, B. H., “A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver”, IEEE Journal of Solid-State Circuits, 2021.
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X. Shen, Duvvuri, D., Bassirian, P., Bishop, H. L., Liu, X., Dissanayake, A., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A 184 nW, -78.3 dBm Sensitivity Antenna-Coupled Supply, Temperature, and Interference-Robust Wake-up Receiver at 4.9 GHz”, IEEE Transactions on Microwave Theory and Techniques, 2022.
A. Dissanayake, Moody, J., Bishop, H. L., Truesdell, D. S., Muhlbauer, H., Lu, R., Gao, A., Gong, S., Calhoun, B. H., and Bowers, S. M., “A -108dBm Sensitivity, -28dB SIR, 130nW to 41μW, Digitally Reconfigurable Bit-Level Duty-Cycled Wakeup and Data Receiver”, in IEEE Custom Integrated Circuits Conference (CICC), 2020.
J. Moody, Dissanayake, A., Bishop, H., Lu, R., Liu, N. X., Duvvuri, D., Gao, A., Truesdell, D. S., N. Barker, S., Gong, S., Calhoun, B. H., and Bowers, S. M., “A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver”, in 2019 Symposium on VLSI Circuits, Kyoto, Japan, 2019.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102dBm Sensitivity, 2.2µA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR”, in IEEE Custom Integrated Circuits Conference (CICC), 2023.
L. Zhang, Duvvuri, D., Bhattacharya, S., Dissanayake, A., Liu, X., Bishop, H. L., Zhang, Y., Blalock, T. N., Calhoun, B. H., and Bowers, S. M., “A -102 dBm Sensitivity Multi-Channel Heterodyne Wake-Up Receiver with Integrated ADPLL”, IEEE Open Journal of the Solid-State Circuits Society, 2024.
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R. Agarwala, Wang, P., Bishop, H. L., Dissanayake, A., and Calhoun, B. H., “A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring”, IEEE Journal of Solid-State Circuits, 2021.
D. S. Truesdell, Dissanayake, A., and Calhoun, B. H., “A 0.6-V 44.6-fJ/Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm/°C Stability”, IEEE Solid-State Circuits Letters (SSCL), 2019.PDF icon A 0.6-V 44.6-fJ Cycle Energy-Optimized Frequency-Locked Loop in 65-nm CMOS With 20.3-ppm C Stability.pdf (1.64 MB)